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-rw-r--r--src/soc/qualcomm/sc7180/Makefile.inc4
-rw-r--r--src/soc/qualcomm/sc7180/bootblock.c2
-rw-r--r--src/soc/qualcomm/sc7180/include/soc/addressmap.h21
-rw-r--r--src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h467
-rw-r--r--src/soc/qualcomm/sc7180/include/soc/qupv3_config.h80
-rw-r--r--src/soc/qualcomm/sc7180/qcom_qup_se.c258
-rw-r--r--src/soc/qualcomm/sc7180/qupv3_config.c219
7 files changed, 1051 insertions, 0 deletions
diff --git a/src/soc/qualcomm/sc7180/Makefile.inc b/src/soc/qualcomm/sc7180/Makefile.inc
index 5f4dc1d756..554efd8801 100644
--- a/src/soc/qualcomm/sc7180/Makefile.inc
+++ b/src/soc/qualcomm/sc7180/Makefile.inc
@@ -10,6 +10,8 @@ bootblock-y += gpio.c
bootblock-$(CONFIG_DRIVERS_UART) += uart_bitbang.c
bootblock-y += clock.c
bootblock-$(CONFIG_SC7180_QSPI) += qspi.c
+bootblock-y += qupv3_config.c
+bootblock-y += qcom_qup_se.c
################################################################################
verstage-y += timer.c
@@ -43,6 +45,8 @@ ramstage-y += clock.c
ramstage-$(CONFIG_SC7180_QSPI) += qspi.c
ramstage-y += aop_load_reset.c
ramstage-y += usb.c
+ramstage-y += qupv3_config.c
+ramstage-y += qcom_qup_se.c
################################################################################
diff --git a/src/soc/qualcomm/sc7180/bootblock.c b/src/soc/qualcomm/sc7180/bootblock.c
index 29348c2a24..9cecb4f4f5 100644
--- a/src/soc/qualcomm/sc7180/bootblock.c
+++ b/src/soc/qualcomm/sc7180/bootblock.c
@@ -16,10 +16,12 @@
#include <soc/clock.h>
#include <soc/mmu.h>
#include <soc/qspi.h>
+#include <soc/qupv3_config.h>
void bootblock_soc_init(void)
{
sc7180_mmu_init();
clock_init();
quadspi_init(25 * MHz);
+ qupv3_fw_init();
}
diff --git a/src/soc/qualcomm/sc7180/include/soc/addressmap.h b/src/soc/qualcomm/sc7180/include/soc/addressmap.h
index 5ca34a6380..6ce7b9b185 100644
--- a/src/soc/qualcomm/sc7180/include/soc/addressmap.h
+++ b/src/soc/qualcomm/sc7180/include/soc/addressmap.h
@@ -25,6 +25,27 @@
#define TLMM_WEST_TILE_BASE 0x03500000
/*
+ * QUP SERIAL ENGINE BASE ADDRESSES
+ */
+/* QUPV3_0 */
+#define QUP_SERIAL0_BASE 0x00880000
+#define QUP_SERIAL1_BASE 0x00884000
+#define QUP_SERIAL2_BASE 0x00888000
+#define QUP_SERIAL3_BASE 0x0088C000
+#define QUP_SERIAL4_BASE 0x00890000
+#define QUP_SERIAL5_BASE 0x00894000
+#define QUP_WRAP0_BASE 0x008C0000
+
+/* QUPV3_1 */
+#define QUP_SERIAL6_BASE 0x00A80000
+#define QUP_SERIAL7_BASE 0x00A84000
+#define QUP_SERIAL8_BASE 0x00A88000
+#define QUP_SERIAL9_BASE 0x00A8C000
+#define QUP_SERIAL10_BASE 0x00A90000
+#define QUP_SERIAL11_BASE 0x00A94000
+#define QUP_WRAP1_BASE 0x00AC0000
+
+/*
* USB BASE ADDRESSES
*/
#define QFPROM_BASE 0x00780000
diff --git a/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h
new file mode 100644
index 0000000000..051af9c0b0
--- /dev/null
+++ b/src/soc/qualcomm/sc7180/include/soc/qcom_qup_se.h
@@ -0,0 +1,467 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2018-2019 Qualcomm Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SOC_QCOM_QUP_SE_H__
+#define __SOC_QCOM_QUP_SE_H__
+
+#include <console/console.h>
+#include <device/mmio.h>
+#include <gpio.h>
+#include <soc/addressmap.h>
+#include <stdint.h>
+#include <timer.h>
+
+#define GENMASK(h, l) (BIT(h + 1) - BIT(l))
+
+/* GENI_OUTPUT_CTRL fields */
+#define DEFAULT_IO_OUTPUT_CTRL_MSK GENMASK(6, 0)
+
+/* GENI_FORCE_DEFAULT_REG fields */
+#define FORCE_DEFAULT BIT(0)
+
+#define GENI_FW_REVISION_RO_PROTOCOL_MASK 0x0000FF00
+#define GENI_FW_REVISION_RO_PROTOCOL_SHIFT 0x00000008
+
+/* GENI_CGC_CTRL fields */
+#define CFG_AHB_CLK_CGC_ON BIT(0)
+#define CFG_AHB_WR_ACLK_CGC_ON BIT(1)
+#define DATA_AHB_CLK_CGC_ON BIT(2)
+#define SCLK_CGC_ON BIT(3)
+#define TX_CLK_CGC_ON BIT(4)
+#define RX_CLK_CGC_ON BIT(5)
+#define EXT_CLK_CGC_ON BIT(6)
+#define PROG_RAM_HCLK_OFF BIT(8)
+#define PROG_RAM_SCLK_OFF BIT(9)
+#define DEFAULT_CGC_EN (CFG_AHB_CLK_CGC_ON | CFG_AHB_WR_ACLK_CGC_ON \
+ | DATA_AHB_CLK_CGC_ON | SCLK_CGC_ON \
+ | TX_CLK_CGC_ON | RX_CLK_CGC_ON | EXT_CLK_CGC_ON)
+
+/* GENI_SER_M_CLK_CFG/GENI_SER_S_CLK_CFG */
+#define SER_CLK_EN BIT(0)
+#define CLK_DIV_SHFT 4
+#define CLK_DIV_MSK (0xFFF << CLK_DIV_SHFT)
+
+/* FIFO_IF_DISABLE_RO fields */
+#define FIFO_IF_DISABLE BIT(0)
+
+/* FW_REVISION_RO fields */
+#define FW_REV_PROTOCOL_MSK GENMASK(15, 8)
+#define FW_REV_PROTOCOL_SHFT 8
+#define FW_REV_VERSION_SHFT 0
+
+/* GENI_CLK_SEL fields */
+#define CLK_SEL_MSK GENMASK(2, 0)
+
+/* SE_GENI_DMA_MODE_EN */
+#define GENI_DMA_MODE_EN BIT(0)
+
+/* GENI_M_CMD0 fields */
+#define M_OPCODE_MSK GENMASK(31, 27)
+#define M_OPCODE_SHFT 27
+#define M_PARAMS_MSK GENMASK(26, 0)
+
+/* GENI_M_CMD_CTRL_REG */
+#define M_GENI_CMD_CANCEL BIT(2)
+#define M_GENI_CMD_ABORT BIT(1)
+#define M_GENI_DISABLE BIT(0)
+
+/* GENI_S_CMD0 fields */
+#define S_OPCODE_MSK GENMASK(31, 27)
+#define S_OPCODE_SHFT 27
+#define S_PARAMS_MSK GENMASK(26, 0)
+
+/* GENI_S_CMD_CTRL_REG */
+#define S_GENI_CMD_CANCEL BIT(2)
+#define S_GENI_CMD_ABORT BIT(1)
+#define S_GENI_DISABLE BIT(0)
+
+/* GENI_M_IRQ_EN fields */
+#define M_CMD_DONE_EN BIT(0)
+#define M_CMD_OVERRUN_EN BIT(1)
+#define M_ILLEGAL_CMD_EN BIT(2)
+#define M_CMD_FAILURE_EN BIT(3)
+#define M_CMD_CANCEL_EN BIT(4)
+#define M_CMD_ABORT_EN BIT(5)
+#define M_TIMESTAMP_EN BIT(6)
+#define M_RX_IRQ_EN BIT(7)
+#define M_GP_SYNC_IRQ_0_EN BIT(8)
+#define M_GP_IRQ_0_EN BIT(9)
+#define M_GP_IRQ_1_EN BIT(10)
+#define M_GP_IRQ_2_EN BIT(11)
+#define M_GP_IRQ_3_EN BIT(12)
+#define M_GP_IRQ_4_EN BIT(13)
+#define M_GP_IRQ_5_EN BIT(14)
+#define M_IO_DATA_DEASSERT_EN BIT(22)
+#define M_IO_DATA_ASSERT_EN BIT(23)
+#define M_RX_FIFO_RD_ERR_EN BIT(24)
+#define M_RX_FIFO_WR_ERR_EN BIT(25)
+#define M_RX_FIFO_WATERMARK_EN BIT(26)
+#define M_RX_FIFO_LAST_EN BIT(27)
+#define M_TX_FIFO_RD_ERR_EN BIT(28)
+#define M_TX_FIFO_WR_ERR_EN BIT(29)
+#define M_TX_FIFO_WATERMARK_EN BIT(30)
+#define M_SEC_IRQ_EN BIT(31)
+#define M_COMMON_GENI_M_IRQ_EN (GENMASK(6, 1) | \
+ M_IO_DATA_DEASSERT_EN | \
+ M_IO_DATA_ASSERT_EN | M_RX_FIFO_RD_ERR_EN | \
+ M_RX_FIFO_WR_ERR_EN | M_TX_FIFO_RD_ERR_EN | \
+ M_TX_FIFO_WR_ERR_EN)
+
+/* GENI_S_IRQ_EN fields */
+#define S_CMD_DONE_EN BIT(0)
+#define S_CMD_OVERRUN_EN BIT(1)
+#define S_ILLEGAL_CMD_EN BIT(2)
+#define S_CMD_FAILURE_EN BIT(3)
+#define S_CMD_CANCEL_EN BIT(4)
+#define S_CMD_ABORT_EN BIT(5)
+#define S_GP_SYNC_IRQ_0_EN BIT(8)
+#define S_GP_IRQ_0_EN BIT(9)
+#define S_GP_IRQ_1_EN BIT(10)
+#define S_GP_IRQ_2_EN BIT(11)
+#define S_GP_IRQ_3_EN BIT(12)
+#define S_GP_IRQ_4_EN BIT(13)
+#define S_GP_IRQ_5_EN BIT(14)
+#define S_IO_DATA_DEASSERT_EN BIT(22)
+#define S_IO_DATA_ASSERT_EN BIT(23)
+#define S_RX_FIFO_RD_ERR_EN BIT(24)
+#define S_RX_FIFO_WR_ERR_EN BIT(25)
+#define S_RX_FIFO_WATERMARK_EN BIT(26)
+#define S_RX_FIFO_LAST_EN BIT(27)
+#define S_COMMON_GENI_S_IRQ_EN (GENMASK(5, 1) | GENMASK(13, 9) | \
+ S_RX_FIFO_RD_ERR_EN | S_RX_FIFO_WR_ERR_EN)
+
+/* GENI_/TX/RX/RX_RFR/_WATERMARK_REG fields */
+#define WATERMARK_MSK GENMASK(5, 0)
+
+/* GENI_TX_FIFO_STATUS fields */
+#define TX_FIFO_WC GENMASK(27, 0)
+
+/* GENI_RX_FIFO_STATUS fields */
+#define RX_LAST BIT(31)
+#define RX_LAST_BYTE_VALID_MSK GENMASK(30, 28)
+#define RX_LAST_BYTE_VALID_SHFT 28
+#define RX_FIFO_WC_MSK GENMASK(24, 0)
+
+/* SE_IRQ_EN fields */
+#define DMA_RX_IRQ_EN BIT(0)
+#define DMA_TX_IRQ_EN BIT(1)
+#define GENI_M_IRQ_EN BIT(2)
+#define GENI_S_IRQ_EN BIT(3)
+
+/* SE_DMA_GENERAL_CFG */
+#define DMA_RX_CLK_CGC_ON BIT(0)
+#define DMA_TX_CLK_CGC_ON BIT(1)
+#define DMA_AHB_SLV_CFG_ON BIT(2)
+#define AHB_SEC_SLV_CLK_CGC_ON BIT(3)
+#define DUMMY_RX_NON_BUFFERABLE BIT(4)
+#define RX_DMA_ZERO_PADDING_EN BIT(5)
+#define RX_DMA_IRQ_DELAY_MSK GENMASK(8, 6)
+#define RX_DMA_IRQ_DELAY_SHFT 6
+
+#define DEFAULT_SE_CLK (19200 * KHz)
+#define GENI_DFS_IF_CFG_DFS_IF_EN_BMSK BIT(0)
+
+/* FIFO BUFFER PARAMETERS */
+#define BYTES_PER_FIFO_WORD 4
+#define FIFO_WIDTH 32
+#define FIFO_DEPTH 16
+#define BITS_PER_WORD 8
+#define TX_WATERMARK 1
+
+/* PACKING CONFIGURATION VECTOR */
+
+/* start_idx:x: Bit position to move
+ * direction:1: MSB to LSB
+ * len:7: Represents bits-per-word = 8
+ * stop:0: Till it's 1, FIFO bit shift continues
+ */
+
+/* Start_idx:7, direction:1, len:7, stop:0 */
+#define PACK_VECTOR0 0x0FE
+/* Start_idx:15, direction:1, len:7, stop:0 */
+#define PACK_VECTOR1 0x1FE
+/* Start_idx:23, direction:1, len:7, stop:0 */
+#define PACK_VECTOR2 0x2FE
+/* Start_idx:31, direction:1, len:7, stop:1 */
+#define PACK_VECTOR3 0x3FF
+
+enum qup_se {
+ QUPV3_0_SE0,
+ QUPV3_0_SE1,
+ QUPV3_0_SE2,
+ QUPV3_0_SE3,
+ QUPV3_0_SE4,
+ QUPV3_0_SE5,
+ QUPV3_1_SE0,
+ QUPV3_1_SE1,
+ QUPV3_1_SE2,
+ QUPV3_1_SE3,
+ QUPV3_1_SE4,
+ QUPV3_1_SE5,
+ QUPV3_SE_MAX,
+};
+
+enum se_protocol {
+ SE_PROTOCOL_SPI = 1,
+ SE_PROTOCOL_UART = 2,
+ SE_PROTOCOL_I2C = 3,
+ SE_PROTOCOL_I3C = 4,
+ SE_PROTOCOL_MAX = 5
+};
+
+enum se_mode {
+ NONE,
+ GSI,
+ FIFO,
+ CPU_DMA,
+ MIXED
+};
+
+struct qup_regs {
+ u32 geni_init_cfg_revision;
+ u32 geni_s_init_cfg_revision;
+ u8 _reserved1[0x10 - 0x08];
+ u32 geni_general_cfg;
+ u32 geni_rx_fifo_ctrl;
+ u8 _reserved2[0x20 - 0x18];
+ u32 geni_force_default_reg;
+ u32 geni_output_ctrl;
+ u32 geni_cgc_ctrl;
+ u32 geni_char_cfg;
+ u32 geni_char_data_n;
+ u8 _reserved3[0x40 - 0x34];
+ u32 geni_status;
+ u32 geni_test_bus_ctrl;
+ u32 geni_ser_m_clk_cfg;
+ u32 geni_ser_s_clk_cfg;
+ u32 geni_prog_rom_ctrl_reg;
+ u8 _reserved4[0x60 - 0x54];
+ u32 geni_clk_ctrl_ro;
+ u32 fifo_if_disable_ro;
+ u32 geni_fw_revision_ro;
+ u32 geni_s_fw_revision_ro;
+ u32 geni_fw_multilock_protns_ro;
+ u32 geni_fw_multilock_msa_ro;
+ u32 geni_fw_multilock_sp_ro;
+ u32 geni_clk_sel;
+ u32 geni_dfs_if_cfg;
+ u8 _reserved5[0x100 - 0x084];
+ u32 geni_cfg_reg0;
+ u32 geni_cfg_reg1;
+ u32 geni_cfg_reg2;
+ u32 geni_cfg_reg3;
+ u32 geni_cfg_reg4;
+ u32 geni_cfg_reg5;
+ u32 geni_cfg_reg6;
+ u32 geni_cfg_reg7;
+ u32 geni_cfg_reg8;
+ u32 geni_cfg_reg9;
+ u32 geni_cfg_reg10;
+ u32 geni_cfg_reg11;
+ u32 geni_cfg_reg12;
+ u32 geni_cfg_reg13;
+ u32 geni_cfg_reg14;
+ u32 geni_cfg_reg15;
+ u32 geni_cfg_reg16;
+ u32 geni_cfg_reg17;
+ u32 geni_cfg_reg18;
+ u8 _reserved6[0x200 - 0x14C];
+ u32 geni_cfg_reg64;
+ u32 geni_cfg_reg65;
+ u32 geni_cfg_reg66;
+ u32 geni_cfg_reg67;
+ u32 geni_cfg_reg68;
+ u32 geni_cfg_reg69;
+ u32 geni_cfg_reg70;
+ u32 geni_cfg_reg71;
+ u32 geni_cfg_reg72;
+ u32 spi_cpha;
+ u32 geni_cfg_reg74;
+ u32 proto_loopback_cfg;
+ u32 spi_cpol;
+ u32 i2c_noise_cancellation_ctl;
+ u32 i2c_monitor_ctl;
+ u32 geni_cfg_reg79;
+ u32 geni_cfg_reg80;
+ u32 geni_cfg_reg81;
+ u32 geni_cfg_reg82;
+ u32 spi_demux_output_inv;
+ u32 spi_demux_sel;
+ u32 geni_byte_granularity;
+ u32 geni_dma_mode_en;
+ u32 uart_tx_trans_cfg_reg;
+ u32 geni_tx_packing_cfg0;
+ u32 geni_tx_packing_cfg1;
+ union {
+ u32 uart_tx_word_len;
+ u32 spi_word_len;
+ };
+ union {
+ u32 uart_tx_stop_bit_len;
+ u32 i2c_tx_trans_len;
+ u32 spi_tx_trans_len;
+ };
+ union {
+ u32 uart_tx_trans_len;
+ u32 i2c_rx_trans_len;
+ u32 spi_rx_trans_len;
+ };
+ u32 spi_pre_post_cmd_dly;
+ u32 i2c_scl_counters;
+ u32 geni_cfg_reg95;
+ u32 uart_rx_trans_cfg;
+ u32 geni_rx_packing_cfg0;
+ u32 geni_rx_packing_cfg1;
+ u32 uart_rx_word_len;
+ u32 geni_cfg_reg100;
+ u32 uart_rx_stale_cnt;
+ u32 geni_cfg_reg102;
+ u32 geni_cfg_reg103;
+ u32 geni_cfg_reg104;
+ u32 uart_tx_parity_cfg;
+ u32 uart_rx_parity_cfg;
+ u32 uart_manual_rfr;
+ u32 geni_cfg_reg108;
+ u32 geni_cfg_reg109;
+ u32 geni_cfg_reg110;
+ u8 _reserved7[0x600 - 0x2BC];
+ u32 geni_m_cmd0;
+ u32 geni_m_cmd_ctrl_reg;
+ u8 _reserved8[0x10 - 0x08];
+ u32 geni_m_irq_status;
+ u32 geni_m_irq_enable;
+ u32 geni_m_irq_clear;
+ u32 geni_m_irq_en_set;
+ u32 geni_m_irq_en_clear;
+ u32 geni_m_cmd_err_status;
+ u32 geni_m_fw_err_status;
+ u8 _reserved9[0x30 - 0x2C];
+ u32 geni_s_cmd0;
+ u32 geni_s_cmd_ctrl_reg;
+ u8 _reserved10[0x40 - 0x38];
+ u32 geni_s_irq_status;
+ u32 geni_s_irq_enable;
+ u32 geni_s_irq_clear;
+ u32 geni_s_irq_en_set;
+ u32 geni_s_irq_en_clear;
+ u8 _reserved11[0x700 - 0x654];
+ u32 geni_tx_fifon;
+ u8 _reserved12[0x780 - 0x704];
+ u32 geni_rx_fifon;
+ u8 _reserved13[0x800 - 0x784];
+ u32 geni_tx_fifo_status;
+ u32 geni_rx_fifo_status;
+ u32 geni_tx_fifo_threshold;
+ u32 geni_tx_watermark_reg;
+ u32 geni_rx_watermark_reg;
+ u32 geni_rx_rfr_watermark_reg;
+ u8 _reserved14[0x900 - 0x818];
+ u32 geni_gp_output_reg;
+ u8 _reserved15[0x908 - 0x904];
+ u32 geni_ios;
+ u32 geni_timestamp;
+ u32 geni_m_gp_length;
+ u32 geni_s_gp_length;
+ u8 _reserved16[0x920 - 0x918];
+ u32 geni_hw_irq_en;
+ u32 geni_hw_irq_ignore_on_active;
+ u8 _reserved17[0x930 - 0x928];
+ u32 geni_hw_irq_cmd_param_0;
+ u8 _reserved18[0xA00 - 0x934];
+ u32 geni_i3c_ibi_cfg_tablen;
+ u8 _reserved19[0xA80 - 0xA04];
+ u32 geni_i3c_ibi_status;
+ u32 geni_i3c_ibi_rd_data;
+ u32 geni_i3c_ibi_search_pattern;
+ u32 geni_i3c_ibi_search_data;
+ u32 geni_i3c_sw_ibi_en;
+ u32 geni_i3c_sw_ibi_en_recover;
+ u8 _reserved20[0xC30 - 0xA98];
+ u32 dma_tx_ptr_l;
+ u32 dma_tx_ptr_h;
+ u32 dma_tx_attr;
+ u32 dma_tx_length;
+ u32 dma_tx_irq_stat;
+ u32 dma_tx_irq_clr;
+ u32 dma_tx_irq_en;
+ u32 dma_tx_irq_en_set;
+ u32 dma_tx_irq_en_clr;
+ u32 dma_tx_length_in;
+ u32 dma_tx_fsm_rst;
+ u32 dma_tx_max_burst_size;
+ u8 _reserved21[0xD30 - 0xC60];
+ u32 dma_rx_ptr_l;
+ u32 dma_rx_ptr_h;
+ u32 dma_rx_attr;
+ u32 dma_rx_length;
+ u32 dma_rx_irq_stat;
+ u32 dma_rx_irq_clr;
+ u32 dma_rx_irq_en;
+ u32 dma_rx_irq_en_set;
+ u32 dma_rx_irq_en_clr;
+ u32 dma_rx_length_in;
+ u32 dma_rx_fsm_rst;
+ u32 dma_rx_max_burst_size;
+ u32 dma_rx_flush;
+ u8 _reserved22[0xE14 - 0xD64];
+ u32 se_irq_high_priority;
+ u32 se_gsi_event_en;
+ u32 se_irq_en;
+ u32 dma_if_en_ro;
+ u32 se_hw_param_0;
+ u32 se_hw_param_1;
+ u32 se_hw_param_2;
+ u32 dma_general_cfg;
+ u8 _reserved23[0x40 - 0x34];
+ u32 dma_debug_reg0;
+ u32 dma_test_bus_ctrl;
+ u32 se_top_test_bus_ctrl;
+ u8 _reserved24[0x1000 - 0x0E4C];
+ u32 se_geni_fw_revision;
+ u32 se_s_fw_revision;
+ u8 _reserved25[0x10-0x08];
+ u32 se_geni_cfg_ramn;
+ u8 _reserved26[0x2000 - 0x1014];
+ u32 se_geni_clk_ctrl;
+ u32 se_dma_if_en;
+ u32 se_fifo_if_disable;
+ u32 se_geni_fw_multilock_protns;
+ u32 se_geni_fw_multilock_msa;
+ u32 se_geni_fw_multilock_sp;
+};
+check_member(qup_regs, geni_clk_sel, 0x7C);
+check_member(qup_regs, geni_cfg_reg108, 0x2B0);
+check_member(qup_regs, geni_dma_mode_en, 0x258);
+check_member(qup_regs, geni_i3c_ibi_rd_data, 0xA84);
+check_member(qup_regs, dma_test_bus_ctrl, 0xE44);
+check_member(qup_regs, se_geni_cfg_ramn, 0x1010);
+check_member(qup_regs, se_geni_fw_multilock_sp, 0x2014);
+
+struct qup {
+ struct qup_regs *regs;
+ gpio_t pin[6];
+ u8 func[6];
+};
+
+extern struct qup qup[12];
+
+u32 qup_wait_for_m_irq(unsigned int bus);
+u32 qup_wait_for_s_irq(unsigned int bus);
+void qup_m_cancel_and_abort(unsigned int bus);
+void qup_s_cancel_and_abort(unsigned int bus);
+int qup_handle_transfer(unsigned int bus, const void *dout, void *din,
+ int size);
+
+#endif /* __SOC_QCOM_QUP_SE_H__ */
diff --git a/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h b/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h
new file mode 100644
index 0000000000..b2a89a53c0
--- /dev/null
+++ b/src/soc/qualcomm/sc7180/include/soc/qupv3_config.h
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _SC7180_QUPV3_CONFIG_H_
+#define _SC7180_QUPV3_CONFIG_H_
+
+#include <assert.h>
+#include <cbfs.h>
+#include <soc/clock.h>
+#include <soc/qcom_qup_se.h>
+
+#define QUPV3_COMMON_CFG_FAST_SWITCH_TO_HIGH_DISABLE_BMSK 0x00000001
+#define QUPV3_SE_AHB_M_CFG_AHB_M_CLK_CGC_ON_BMSK 0x00000001
+
+#define GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK 0x00000200
+#define GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK 0x00000100
+
+#define GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK 0x00000001
+
+#define DMA_TX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK 0x00000008
+#define DMA_TX_IRQ_EN_SET_SBE_EN_SET_BMSK 0x00000004
+#define DMA_TX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK 0x00000001
+
+#define DMA_RX_IRQ_EN_SET_FLUSH_DONE_EN_SET_BMSK 0x00000010
+#define DMA_RX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK 0x00000008
+#define DMA_RX_IRQ_EN_SET_SBE_EN_SET_BMSK 0x00000004
+#define DMA_RX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK 0x00000001
+
+#define DMA_GENERAL_CFG_AHB_SEC_SLV_CLK_CGC_ON_BMSK 0x00000008
+#define DMA_GENERAL_CFG_DMA_AHB_SLV_CLK_CGC_ON_BMSK 0x00000004
+#define DMA_GENERAL_CFG_DMA_TX_CLK_CGC_ON_BMSK 0x00000002
+#define DMA_GENERAL_CFG_DMA_RX_CLK_CGC_ON_BMSK 0x00000001
+
+#define GENI_CLK_CTRL_SER_CLK_SEL_BMSK 0x00000001
+#define DMA_IF_EN_DMA_IF_EN_BMSK 0x00000001
+#define SE_GSI_EVENT_EN_BMSK 0x0000000f
+#define SE_IRQ_EN_RMSK 0x0000000f
+
+#define SIZE_GENI_FW_RAM 0x00000200
+#define MAX_OFFSET_CFG_REG 0x000001c0
+#define SEFW_MAGIC_HEADER 0x57464553
+
+struct elf_se_hdr {
+ uint32_t magic; /* = 'SEFW' */
+ uint32_t version; /* Structure version number */
+ uint32_t core_version; /* QUPV3_HW_VERSION */
+ uint16_t serial_protocol; /* Programmed into GENI_FW_REVISION */
+ uint16_t fw_version; /* Programmed into GENI_FW_REVISION */
+ uint16_t cfg_version; /* Programmed into GENI_INIT_CFG_REVISION */
+ uint16_t fw_size_in_items; /* Number of (uint32_t) GENI_FW_RAM words */
+ uint16_t fw_offset; /* Byte offset of GENI_FW_RAM array */
+ uint16_t cfg_size_in_items;/* Number of GENI_FW_CFG index/value pairs */
+ uint16_t cfg_idx_offset; /* Byte offset of GENI_FW_CFG index array */
+ uint16_t cfg_val_offset; /* Byte offset of GENI_FW_CFG values array */
+};
+
+struct qupv3_common_reg {
+ u8 reserved_1[0x118];
+ u32 qupv3_se_ahb_m_cfg_reg;
+ u8 reserved_2[0x4];
+ u32 qupv3_common_cfg_reg;
+};
+
+void qupv3_fw_init(void);
+void qupv3_se_fw_load_and_init(unsigned int bus, unsigned int protocol,
+ unsigned int mode);
+
+#endif /* _SC7180_QUPV3_CONFIG_H_ */
diff --git a/src/soc/qualcomm/sc7180/qcom_qup_se.c b/src/soc/qualcomm/sc7180/qcom_qup_se.c
new file mode 100644
index 0000000000..b6540a88cf
--- /dev/null
+++ b/src/soc/qualcomm/sc7180/qcom_qup_se.c
@@ -0,0 +1,258 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (c) 2018-2019 Qualcomm Technologies
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/qcom_qup_se.h>
+
+struct qup qup[12] = {
+ [0] = { .regs = (void *)QUP_SERIAL0_BASE,
+ .pin = { GPIO(34), GPIO(35), GPIO(36), GPIO(37) },
+ .func = { GPIO34_FUNC_QUP0_L0, GPIO35_FUNC_QUP0_L1,
+ GPIO36_FUNC_QUP0_L2, GPIO37_FUNC_QUP0_L3 }
+ },
+ [1] = { .regs = (void *)QUP_SERIAL1_BASE,
+ .pin = { GPIO(0), GPIO(1), GPIO(2), GPIO(3),
+ GPIO(12), GPIO(94) },
+ .func = { GPIO0_FUNC_QUP0_L0, GPIO1_FUNC_QUP0_L1,
+ GPIO2_FUNC_QUP0_L2, GPIO3_FUNC_QUP0_L3,
+ GPIO12_FUNC_QUP0_L4, GPIO94_FUNC_QUP0_L5 }
+ },
+ [2] = { .regs = (void *)QUP_SERIAL2_BASE,
+ .pin = { GPIO(15), GPIO(16) },
+ .func = { GPIO15_FUNC_QUP0_L0, GPIO16_FUNC_QUP0_L1 }
+ },
+ [3] = { .regs = (void *)QUP_SERIAL3_BASE,
+ .pin = { GPIO(38), GPIO(39), GPIO(40), GPIO(41) },
+ .func = { GPIO38_FUNC_QUP0_L0, GPIO39_FUNC_QUP0_L1,
+ GPIO40_FUNC_QUP0_L2, GPIO41_FUNC_QUP0_L3 }
+ },
+ [4] = { .regs = (void *)QUP_SERIAL4_BASE,
+ .pin = { GPIO(115), GPIO(116) },
+ .func = { GPIO115_FUNC_QUP0_L0, GPIO116_FUNC_QUP0_L1 }
+ },
+ [5] = { .regs = (void *)QUP_SERIAL5_BASE,
+ .pin = { GPIO(25), GPIO(26), GPIO(27), GPIO(28) },
+ .func = { GPIO25_FUNC_QUP0_L0, GPIO26_FUNC_QUP0_L1,
+ GPIO27_FUNC_QUP0_L2, GPIO28_FUNC_QUP0_L3 }
+ },
+ [6] = { .regs = (void *)QUP_SERIAL6_BASE,
+ .pin = { GPIO(59), GPIO(60), GPIO(61), GPIO(62),
+ GPIO(68), GPIO(72) },
+ .func = { GPIO59_FUNC_QUP1_L0, GPIO60_FUNC_QUP1_L1,
+ GPIO61_FUNC_QUP1_L2, GPIO62_FUNC_QUP1_L3,
+ GPIO68_FUNC_QUP1_L4, GPIO72_FUNC_QUP1_L5 }
+ },
+ [7] = { .regs = (void *)QUP_SERIAL7_BASE,
+ .pin = { GPIO(6), GPIO(7) },
+ .func = { GPIO6_FUNC_QUP1_L0, GPIO7_FUNC_QUP1_L1 }
+ },
+ [8] = { .regs = (void *)QUP_SERIAL8_BASE,
+ .pin = { GPIO(42), GPIO(43), GPIO(44), GPIO(45) },
+ .func = { GPIO42_FUNC_QUP1_L0, GPIO43_FUNC_QUP1_L1,
+ GPIO44_FUNC_QUP1_L2, GPIO45_FUNC_QUP1_L3 }
+ },
+ [9] = { .regs = (void *)QUP_SERIAL9_BASE,
+ .pin = { GPIO(46), GPIO(47) },
+ .func = { GPIO46_FUNC_QUP1_L0, GPIO47_FUNC_QUP1_L1 }
+ },
+ [10] = { .regs = (void *)QUP_SERIAL10_BASE,
+ .pin = { GPIO(86), GPIO(87), GPIO(88), GPIO(89),
+ GPIO(90), GPIO(91) },
+ .func = { GPIO86_FUNC_QUP1_L0, GPIO87_FUNC_QUP1_L1,
+ GPIO88_FUNC_QUP1_L2, GPIO89_FUNC_QUP1_L3,
+ GPIO90_FUNC_QUP1_L4, GPIO91_FUNC_QUP1_L5 }
+ },
+ [11] = { .regs = (void *)QUP_SERIAL11_BASE,
+ .pin = { GPIO(53), GPIO(54), GPIO(55), GPIO(56) },
+ .func = { GPIO53_FUNC_QUP1_L0, GPIO54_FUNC_QUP1_L1,
+ GPIO55_FUNC_QUP1_L2, GPIO56_FUNC_QUP1_L3 }
+ },
+};
+
+u32 qup_wait_for_m_irq(unsigned int bus)
+{
+ struct stopwatch sw;
+ unsigned int m_irq = 0;
+ struct qup_regs *regs = qup[bus].regs;
+
+ stopwatch_init_usecs_expire(&sw, 25);
+ while (!stopwatch_expired(&sw)) {
+ m_irq = read32(&regs->geni_m_irq_status);
+ if (m_irq)
+ break;
+ }
+ return m_irq;
+}
+
+u32 qup_wait_for_s_irq(unsigned int bus)
+{
+ struct stopwatch sw;
+ unsigned int s_irq = 0;
+ struct qup_regs *regs = qup[bus].regs;
+
+ stopwatch_init_usecs_expire(&sw, 25);
+ while (!stopwatch_expired(&sw)) {
+ s_irq = read32(&regs->geni_s_irq_status);
+ if (s_irq)
+ break;
+ }
+ return s_irq;
+}
+
+static int handle_tx(unsigned int bus, const u8 *dout,
+ unsigned int tx_rem_bytes)
+{
+ int max_bytes = 0;
+ struct qup_regs *regs = qup[bus].regs;
+
+ max_bytes = (FIFO_DEPTH - TX_WATERMARK) * BYTES_PER_FIFO_WORD;
+ max_bytes = MIN(tx_rem_bytes, max_bytes);
+
+ buffer_to_fifo32((void *)dout, max_bytes, &regs->geni_tx_fifon,
+ 0, BYTES_PER_FIFO_WORD);
+
+ if (tx_rem_bytes == max_bytes)
+ write32(&regs->geni_tx_watermark_reg, 0);
+ return max_bytes;
+}
+
+static int handle_rx(unsigned int bus, u8 *din, unsigned int rx_rem_bytes)
+{
+ struct qup_regs *regs = qup[bus].regs;
+ u32 rx_fifo_status = read32(&regs->geni_rx_fifo_status);
+ int rx_bytes = 0;
+
+ rx_bytes = (rx_fifo_status & RX_FIFO_WC_MSK) * BYTES_PER_FIFO_WORD;
+ rx_bytes = MIN(rx_rem_bytes, rx_bytes);
+
+ buffer_from_fifo32(din, rx_bytes, &regs->geni_rx_fifon,
+ 0, BYTES_PER_FIFO_WORD);
+ return rx_bytes;
+}
+
+void qup_m_cancel_and_abort(unsigned int bus)
+{
+ struct qup_regs *regs = qup[bus].regs;
+ struct stopwatch sw;
+ unsigned int m_irq;
+
+ write32(&regs->geni_tx_watermark_reg, 0);
+ write32(&regs->geni_m_cmd_ctrl_reg, M_GENI_CMD_CANCEL);
+
+ stopwatch_init_msecs_expire(&sw, 100);
+ do {
+ m_irq = qup_wait_for_m_irq(bus);
+ if (m_irq & M_CMD_CANCEL_EN) {
+ write32(&regs->geni_m_irq_clear, m_irq);
+ break;
+ }
+ write32(&regs->geni_m_irq_clear, m_irq);
+ } while (!stopwatch_expired(&sw));
+
+ if (!(m_irq & M_CMD_CANCEL_EN)) {
+ printk(BIOS_INFO, "%s:Cancel failed, Abort the operation\n",
+ __func__);
+
+ write32(&regs->geni_m_cmd_ctrl_reg, M_GENI_CMD_ABORT);
+ stopwatch_init_msecs_expire(&sw, 100);
+ do {
+ m_irq = qup_wait_for_m_irq(bus);
+ if (m_irq & M_CMD_ABORT_EN) {
+ write32(&regs->geni_m_irq_clear, m_irq);
+ break;
+ }
+ write32(&regs->geni_m_irq_clear, m_irq);
+ } while (!stopwatch_expired(&sw));
+
+ if (!(m_irq & M_CMD_ABORT_EN))
+ printk(BIOS_INFO, "%s:Abort failed\n", __func__);
+ }
+}
+
+void qup_s_cancel_and_abort(unsigned int bus)
+{
+ struct qup_regs *regs = qup[bus].regs;
+ struct stopwatch sw;
+ unsigned int s_irq;
+ u32 rx_fifo_status;
+ u8 buf[64]; /* FIFO size */
+
+ write32(&regs->geni_tx_watermark_reg, 0);
+ write32(&regs->geni_s_cmd_ctrl_reg, S_GENI_CMD_CANCEL);
+
+ stopwatch_init_msecs_expire(&sw, 100);
+ do {
+ s_irq = qup_wait_for_s_irq(bus);
+ rx_fifo_status = read32(&regs->geni_rx_fifo_status);
+ if (rx_fifo_status & RX_LAST)
+ handle_rx(bus, buf, 64); /* Read whatever data available in FIFO */
+ if (s_irq & S_CMD_CANCEL_EN) {
+ write32(&regs->geni_s_irq_clear, s_irq);
+ break;
+ }
+ write32(&regs->geni_s_irq_clear, s_irq);
+ } while (!stopwatch_expired(&sw));
+
+ if (!(s_irq & S_CMD_CANCEL_EN)) {
+ printk(BIOS_INFO, "%s:Cancel failed, Abort the operation\n",
+ __func__);
+
+ write32(&regs->geni_s_cmd_ctrl_reg, S_GENI_CMD_ABORT);
+ stopwatch_init_msecs_expire(&sw, 100);
+ do {
+ s_irq = qup_wait_for_s_irq(bus);
+ if (s_irq & S_CMD_ABORT_EN) {
+ write32(&regs->geni_s_irq_clear, s_irq);
+ break;
+ }
+ write32(&regs->geni_s_irq_clear, s_irq);
+ } while (!stopwatch_expired(&sw));
+
+ if (!(s_irq & S_CMD_ABORT_EN))
+ printk(BIOS_INFO, "%s:Abort failed\n", __func__);
+ }
+}
+
+int qup_handle_transfer(unsigned int bus, const void *dout, void *din, int size)
+{
+ unsigned int m_irq;
+ struct stopwatch sw;
+ unsigned int rx_rem_bytes = din ? size : 0;
+ unsigned int tx_rem_bytes = dout ? size : 0;
+ struct qup_regs *regs = qup[bus].regs;
+
+ stopwatch_init_msecs_expire(&sw, 1000);
+ do {
+ m_irq = qup_wait_for_m_irq(bus);
+ if ((m_irq & M_RX_FIFO_WATERMARK_EN) ||
+ (m_irq & M_RX_FIFO_LAST_EN))
+ rx_rem_bytes -= handle_rx(bus, din + size
+ - rx_rem_bytes, rx_rem_bytes);
+ if (m_irq & M_TX_FIFO_WATERMARK_EN)
+ tx_rem_bytes -= handle_tx(bus, dout + size
+ - tx_rem_bytes, tx_rem_bytes);
+ if (m_irq & M_CMD_DONE_EN) {
+ write32(&regs->geni_m_irq_clear, m_irq);
+ break;
+ }
+ write32(&regs->geni_m_irq_clear, m_irq);
+ } while (!stopwatch_expired(&sw));
+
+ if (!(m_irq & M_CMD_DONE_EN) || tx_rem_bytes || rx_rem_bytes) {
+ printk(BIOS_INFO, "%s:Error: Transfer failed\n", __func__);
+ qup_m_cancel_and_abort(bus);
+ return -1;
+ }
+ return 0;
+}
diff --git a/src/soc/qualcomm/sc7180/qupv3_config.c b/src/soc/qualcomm/sc7180/qupv3_config.c
new file mode 100644
index 0000000000..14df187886
--- /dev/null
+++ b/src/soc/qualcomm/sc7180/qupv3_config.c
@@ -0,0 +1,219 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020, The Linux Foundation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 and
+ * only version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <soc/qupv3_config.h>
+
+static struct elf_se_hdr *fw_list[SE_PROTOCOL_MAX];
+
+void qupv3_se_fw_load_and_init(unsigned int bus, unsigned int protocol,
+ unsigned int mode)
+{
+ uint32_t i;
+ uint32_t reg_value;
+ const uint8_t *cfg_idx_arr;
+ const uint32_t *cfg_val_arr;
+ const uint32_t *fw_val_arr;
+ struct elf_se_hdr *hdr;
+ struct qup_regs *regs = qup[bus].regs;
+ static const char * const filename[] = {
+ [SE_PROTOCOL_SPI] = "fallback/spi_fw",
+ [SE_PROTOCOL_UART] = "fallback/uart_fw",
+ [SE_PROTOCOL_I2C] = "fallback/i2c_fw",
+ };
+
+ if (protocol >= SE_PROTOCOL_MAX || !filename[protocol])
+ die("*ERROR* * INVALID PROTOCOL ***\n");
+
+ if (!fw_list[protocol]) {
+ fw_list[protocol] = cbfs_boot_map_with_leak(filename[protocol],
+ CBFS_TYPE_RAW, NULL);
+ if (!fw_list[protocol])
+ die("*ERROR* * cbfs_boot_map_with_leak failed ***\n");
+ }
+
+ hdr = fw_list[protocol];
+ assert(hdr->magic == SEFW_MAGIC_HEADER)
+
+ cfg_idx_arr = (const uint8_t *)hdr + hdr->cfg_idx_offset;
+ cfg_val_arr = (const uint32_t *)((uint8_t *)hdr + hdr->cfg_val_offset);
+ fw_val_arr = (const uint32_t *)((uint8_t *)hdr + hdr->fw_offset);
+
+ /* Unlock SE for FW loading */
+ write32(&regs->se_geni_fw_multilock_protns, 0x0);
+ write32(&regs->se_geni_fw_multilock_msa, 0x0);
+
+ /* First, ensure GENI FW is disabled */
+ write32(&regs->geni_output_ctrl, 0x0);
+ clrbits_le32(&regs->geni_dfs_if_cfg, GENI_DFS_IF_CFG_DFS_IF_EN_BMSK);
+ setbits_le32(&regs->geni_cgc_ctrl, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK
+ | GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK);
+ write32(&regs->se_geni_clk_ctrl, 0x0);
+ clrbits_le32(&regs->geni_cgc_ctrl, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK
+ | GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK);
+
+
+ /* HPG section 3.1.7.1 */
+ if (protocol == SE_PROTOCOL_UART) {
+ /* To maintain Div=4 for QcLib, configure clock to 7372800Hz for sc7180 */
+ clock_configure_qup(bus, QUPV3_UART_SRC_HZ);
+ } else {
+ setbits_le32(&regs->geni_dfs_if_cfg,
+ GENI_DFS_IF_CFG_DFS_IF_EN_BMSK);
+ /* configure clock dfsr */
+ clock_configure_dfsr(bus);
+ }
+
+ /* HPG section 3.1.7.2 */
+ /* No Init Required */
+
+ /* HPG section 3.1.7.3 */
+ write32(&regs->dma_general_cfg,
+ DMA_GENERAL_CFG_AHB_SEC_SLV_CLK_CGC_ON_BMSK |
+ DMA_GENERAL_CFG_DMA_AHB_SLV_CLK_CGC_ON_BMSK |
+ DMA_GENERAL_CFG_DMA_TX_CLK_CGC_ON_BMSK |
+ DMA_GENERAL_CFG_DMA_RX_CLK_CGC_ON_BMSK);
+ write32(&regs->geni_cgc_ctrl, DEFAULT_CGC_EN);
+
+ /* HPG section 3.1.7.4 */
+ write32(&regs->geni_init_cfg_revision, hdr->cfg_version);
+ write32(&regs->geni_s_init_cfg_revision, hdr->cfg_version);
+
+ assert(cfg_idx_arr[hdr->cfg_size_in_items - 1] * sizeof(uint32_t) <=
+ MAX_OFFSET_CFG_REG);
+
+ for (i = 0; i < hdr->cfg_size_in_items; i++) {
+ write32(&regs->geni_cfg_reg0 + cfg_idx_arr[i],
+ cfg_val_arr[i]);
+ }
+
+ /* HPG section 3.1.7.9 */
+ /* non-UART configuration, UART driver can configure as desired for UART
+ */
+ write32(&regs->geni_rx_rfr_watermark_reg, FIFO_DEPTH - 2);
+
+ /* HPG section 3.1.7.5 */
+ /* Don't change any SPI polarity, client driver will handle this */
+ setbits_le32(&regs->geni_output_ctrl, DEFAULT_IO_OUTPUT_CTRL_MSK);
+
+ /* HPG section 3.1.7.6 */
+ reg_value = read32(&regs->geni_dma_mode_en);
+ if (mode == GSI) {
+ reg_value |= GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK;
+ write32(&regs->geni_dma_mode_en, reg_value);
+ write32(&regs->se_irq_en, 0x0);
+ write32(&regs->se_gsi_event_en, SE_GSI_EVENT_EN_BMSK);
+ } else if (mode == FIFO) {
+ reg_value &= ~GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK;
+ write32(&regs->geni_dma_mode_en, reg_value);
+ write32(&regs->se_irq_en, SE_IRQ_EN_RMSK);
+ write32(&regs->se_gsi_event_en, 0x0);
+ } else if (mode == CPU_DMA) {
+ reg_value |= GENI_DMA_MODE_EN_GENI_DMA_MODE_EN_BMSK;
+ write32(&regs->geni_dma_mode_en, reg_value);
+ write32(&regs->se_irq_en, SE_IRQ_EN_RMSK);
+ write32(&regs->se_gsi_event_en, 0x0);
+ }
+
+ /* HPG section 3.1.7.7 */
+ write32(&regs->geni_m_irq_enable,
+ M_COMMON_GENI_M_IRQ_EN);
+ reg_value = S_CMD_OVERRUN_EN | S_ILLEGAL_CMD_EN |
+ S_CMD_CANCEL_EN | S_CMD_ABORT_EN |
+ S_GP_IRQ_0_EN | S_GP_IRQ_1_EN |
+ S_GP_IRQ_2_EN | S_GP_IRQ_3_EN |
+ S_RX_FIFO_WR_ERR_EN | S_RX_FIFO_RD_ERR_EN;
+ write32(&regs->geni_s_irq_enable, reg_value);
+
+ /* HPG section 3.1.7.8 */
+ /* GPI/DMA mode */
+ reg_value = DMA_TX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK |
+ DMA_TX_IRQ_EN_SET_SBE_EN_SET_BMSK |
+ DMA_TX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK;
+ write32(&regs->dma_tx_irq_en_set, reg_value);
+
+ reg_value = DMA_RX_IRQ_EN_SET_FLUSH_DONE_EN_SET_BMSK |
+ DMA_RX_IRQ_EN_SET_RESET_DONE_EN_SET_BMSK |
+ DMA_RX_IRQ_EN_SET_SBE_EN_SET_BMSK |
+ DMA_RX_IRQ_EN_SET_DMA_DONE_EN_SET_BMSK;
+ write32(&regs->dma_rx_irq_en_set, reg_value);
+
+ /* HPG section 3.1.7.10 */
+ reg_value = (hdr->serial_protocol << FW_REV_PROTOCOL_SHFT) |
+ (hdr->fw_version & 0xFF <<
+ FW_REV_VERSION_SHFT);
+ write32(&regs->se_geni_fw_revision, reg_value);
+
+ reg_value =
+ (hdr->serial_protocol << FW_REV_PROTOCOL_SHFT) |
+ (hdr->fw_version & 0xFF <<
+ FW_REV_VERSION_SHFT);
+ write32(&regs->se_s_fw_revision, reg_value);
+
+ assert(hdr->fw_size_in_items <= SIZE_GENI_FW_RAM);
+
+ memcpy((&regs->se_geni_cfg_ramn), fw_val_arr,
+ hdr->fw_size_in_items * sizeof(uint32_t));
+
+ /* HPG section 3.1.7.12 */
+ write32(&regs->geni_force_default_reg, 0x1);
+ setbits_le32(&regs->geni_cgc_ctrl, GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK
+ |GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK);
+ setbits_le32(&regs->se_geni_clk_ctrl, GENI_CLK_CTRL_SER_CLK_SEL_BMSK);
+ clrbits_le32(&regs->geni_cgc_ctrl,
+ (GENI_CGC_CTRL_PROG_RAM_SCLK_OFF_BMSK |
+ GENI_CGC_CTRL_PROG_RAM_HCLK_OFF_BMSK));
+
+ /* HPG section 3.1.7.13 */
+ /* GSI/DMA mode */
+ setbits_le32(&regs->se_dma_if_en, DMA_IF_EN_DMA_IF_EN_BMSK);
+
+ /* HPG section 3.1.7.14 */
+ reg_value = read32(&regs->se_fifo_if_disable);
+ if ((mode == MIXED) || (mode == FIFO))
+ reg_value &= ~FIFO_IF_DISABLE;
+ else
+ reg_value |= FIFO_IF_DISABLE;
+ write32(&regs->se_fifo_if_disable, reg_value);
+ write32(&regs->se_geni_clk_ctrl, 0x1);
+
+ /* Lock SE from FW loading */
+ write32(&regs->se_geni_fw_multilock_protns, 0x1);
+ write32(&regs->se_geni_fw_multilock_msa, 0x1);
+}
+
+static void qup_common_init(int addr)
+{
+ struct qupv3_common_reg *qupv3_common;
+ /* HPG section 3.1.2 */
+ qupv3_common = (struct qupv3_common_reg *)(uintptr_t) addr;
+ setbits32(&qupv3_common->qupv3_common_cfg_reg,
+ QUPV3_COMMON_CFG_FAST_SWITCH_TO_HIGH_DISABLE_BMSK);
+
+ /* HPG section 3.1.7.3 */
+ setbits32(&qupv3_common->qupv3_se_ahb_m_cfg_reg,
+ QUPV3_SE_AHB_M_CFG_AHB_M_CLK_CGC_ON_BMSK);
+}
+
+void qupv3_fw_init(void)
+{
+ uint8_t i;
+
+ /* Turn on all QUP clocks */
+ for (i = 0; i < QUPV3_SE_MAX; i++)
+ clock_enable_qup(i);
+
+ qup_common_init(QUP_WRAP0_BASE);
+ qup_common_init(QUP_WRAP1_BASE);
+}
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 09:59:09 +0000