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-rw-r--r--src/soc/intel/xeon_sp/spr/Kconfig9
-rw-r--r--src/soc/intel/xeon_sp/spr/romstage.c17
2 files changed, 26 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/spr/Kconfig b/src/soc/intel/xeon_sp/spr/Kconfig
index 4db0529bc1..308ec2d45e 100644
--- a/src/soc/intel/xeon_sp/spr/Kconfig
+++ b/src/soc/intel/xeon_sp/spr/Kconfig
@@ -173,4 +173,13 @@ config INTEL_TXT_HEAP_SIZE
endif # INTEL_TXT
+config ENABLE_IO_MARGINING
+ bool "Enable IO Margining"
+ default n
+ depends on !PCIEXP_ASPM
+ help
+ Enable support for I/O margining. This is mutually exclusive with
+ ASPM. This option is intended for debugging and validation and
+ should normally be disabled.
+
endif
diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c
index f36e5ccf1c..8f4e98eea4 100644
--- a/src/soc/intel/xeon_sp/spr/romstage.c
+++ b/src/soc/intel/xeon_sp/spr/romstage.c
@@ -200,6 +200,23 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
config_upd_from_vpd(mupd);
initialize_iio_upd(mupd);
mainboard_memory_init_params(mupd);
+
+ if (CONFIG(ENABLE_IO_MARGINING)) {
+ printk(BIOS_INFO, "IO Margining Enabled.\n");
+ /* Needed for IO Margining */
+ mupd->FspmConfig.DFXEnable = 1;
+
+ UPD_IIO_PCIE_PORT_CONFIG *iio_pcie_cfg;
+ int socket;
+
+ iio_pcie_cfg = (UPD_IIO_PCIE_PORT_CONFIG *)mupd->FspmConfig.IioPcieConfigTablePtr;
+
+ for (socket = 0; socket < MAX_SOCKET; socket++)
+ iio_pcie_cfg[socket].PcieGlobalAspm = 0;
+
+ mupd->FspmConfig.KtiLinkL1En = 0;
+ mupd->FspmConfig.KtiLinkL0pEn = 0;
+ }
}
static uint8_t get_error_correction_type(const uint8_t RasModesEnabled)