diff options
| -rw-r--r-- | src/mainboard/google/reef/dsdt.asl | 7 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/acpi/southbridge.asl | 9 |
2 files changed, 10 insertions, 6 deletions
diff --git a/src/mainboard/google/reef/dsdt.asl b/src/mainboard/google/reef/dsdt.asl index 3265941071..bfdd765699 100644 --- a/src/mainboard/google/reef/dsdt.asl +++ b/src/mainboard/google/reef/dsdt.asl @@ -46,7 +46,7 @@ DefinitionBlock( /* Chipset specific sleep states */ #include <soc/intel/apollolake/acpi/sleepstates.asl> - /* LID and Power button. */ + /* LID */ Scope (\_SB) { Device (LID0) @@ -58,11 +58,6 @@ DefinitionBlock( } Name (_PRW, Package () { GPE_EC_WAKE, 0x3 }) } - - Device (PWRB) - { - Name (_HID, EisaId ("PNP0C0C")) - } } /* Chrome OS Embedded Controller */ diff --git a/src/soc/intel/apollolake/acpi/southbridge.asl b/src/soc/intel/apollolake/acpi/southbridge.asl index d7ced0f924..1c10f1a5ed 100644 --- a/src/soc/intel/apollolake/acpi/southbridge.asl +++ b/src/soc/intel/apollolake/acpi/southbridge.asl @@ -17,6 +17,15 @@ #include <soc/gpe.h> +/* Power button. */ +Scope (\_SB) +{ + Device (PWRB) + { + Name (_HID, EisaId ("PNP0C0C")) + } +} + /* PCIE device */ #include "pcie.asl" |