diff options
| -rw-r--r-- | src/cpu/amd/mtrr/amd_mtrr.c | 45 | ||||
| -rw-r--r-- | src/include/cpu/amd/mtrr.h | 14 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family14/northbridge.c | 7 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family15tn/northbridge.c | 9 | ||||
| -rw-r--r-- | src/northbridge/amd/agesa/family16kb/northbridge.c | 9 | ||||
| -rw-r--r-- | src/northbridge/amd/pi/00730F01/northbridge.c | 11 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/chip.c | 1 | ||||
| -rw-r--r-- | src/soc/amd/stoneyridge/northbridge.c | 2 |
8 files changed, 16 insertions, 82 deletions
diff --git a/src/cpu/amd/mtrr/amd_mtrr.c b/src/cpu/amd/mtrr/amd_mtrr.c index 7502ca83ff..d17eedd919 100644 --- a/src/cpu/amd/mtrr/amd_mtrr.c +++ b/src/cpu/amd/mtrr/amd_mtrr.c @@ -3,54 +3,11 @@ #include <amdblocks/biosram.h> #include <console/console.h> #include <device/device.h> -#include <arch/cpu.h> -#include <cpu/cpu.h> -#include <cpu/x86/mtrr.h> -#include <cpu/x86/msr.h> #include <cpu/amd/mtrr.h> -#include <cpu/x86/cache.h> - -/* These will likely move to some device node or cbmem. */ -static uint64_t amd_topmem = 0; -static uint64_t amd_topmem2 = 0; - -uint64_t bsp_topmem(void) -{ - return amd_topmem; -} - -uint64_t bsp_topmem2(void) -{ - return amd_topmem2; -} - -/* Take a copy of BSP CPUs TOP_MEM and TOP_MEM2 registers, - * so they can be distributed to AP CPUs. Not strictly MTRRs, - * but this is not that bad a place to have this code. - */ -void setup_bsp_ramtop(void) -{ - msr_t msr, msr2; - - /* TOP_MEM: the top of DRAM below 4G */ - msr = rdmsr(TOP_MEM); - printk(BIOS_INFO, - "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr.lo, msr.hi); - - /* TOP_MEM2: the top of DRAM above 4G */ - msr2 = rdmsr(TOP_MEM2); - printk(BIOS_INFO, - "%s, TOP MEM2: msr.lo = 0x%08x, msr.hi = 0x%08x\n", - __func__, msr2.lo, msr2.hi); - - amd_topmem = (uint64_t) msr.hi << 32 | msr.lo; - amd_topmem2 = (uint64_t) msr2.hi << 32 | msr2.lo; -} void add_uma_resource_below_tolm(struct device *nb, int idx) { - uint32_t topmem = bsp_topmem(); + uint32_t topmem = amd_topmem(); uint32_t top_of_cacheable = restore_top_of_low_cacheable(); if (top_of_cacheable == topmem) diff --git a/src/include/cpu/amd/mtrr.h b/src/include/cpu/amd/mtrr.h index 9a943ac64f..6fe1628bc0 100644 --- a/src/include/cpu/amd/mtrr.h +++ b/src/include/cpu/amd/mtrr.h @@ -66,10 +66,16 @@ static __always_inline void wrmsr_amd(unsigned int index, msr_t msr) ); } -/* To distribute topmem MSRs to APs. */ -void setup_bsp_ramtop(void); -uint64_t bsp_topmem(void); -uint64_t bsp_topmem2(void); +static inline uint64_t amd_topmem(void) +{ + return rdmsr(TOP_MEM).lo; +} + +static inline uint64_t amd_topmem2(void) +{ + msr_t msr = rdmsr(TOP_MEM2); + return (uint64_t)msr.hi << 32 | msr.lo; +} #endif #endif /* CPU_AMD_MTRR_H */ diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 4aed96b50e..4b4ab679d9 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -818,13 +818,6 @@ static struct device_operations cpu_bus_ops = { static void root_complex_enable_dev(struct device *dev) { - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; diff --git a/src/northbridge/amd/agesa/family15tn/northbridge.c b/src/northbridge/amd/agesa/family15tn/northbridge.c index fe567362f8..bd0a5c8e86 100644 --- a/src/northbridge/amd/agesa/family15tn/northbridge.c +++ b/src/northbridge/amd/agesa/family15tn/northbridge.c @@ -737,7 +737,7 @@ static void domain_set_resources(struct device *dev) sizek = 0; } else { - uint64_t topmem2 = bsp_topmem2(); + uint64_t topmem2 = amd_topmem2(); basek = 4*1024*1024; sizek = topmem2/1024 - basek; } @@ -900,13 +900,6 @@ static struct device_operations cpu_bus_ops = { static void root_complex_enable_dev(struct device *dev) { - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; diff --git a/src/northbridge/amd/agesa/family16kb/northbridge.c b/src/northbridge/amd/agesa/family16kb/northbridge.c index 21b4d69647..3d5313a333 100644 --- a/src/northbridge/amd/agesa/family16kb/northbridge.c +++ b/src/northbridge/amd/agesa/family16kb/northbridge.c @@ -750,7 +750,7 @@ static void domain_set_resources(struct device *dev) sizek = 0; } else { - uint64_t topmem2 = bsp_topmem2(); + uint64_t topmem2 = amd_topmem2(); basek = 4*1024*1024; sizek = topmem2/1024 - basek; } @@ -922,13 +922,6 @@ static struct device_operations cpu_bus_ops = { static void root_complex_enable_dev(struct device *dev) { - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index f1c5e23657..332bf1ac2a 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -770,7 +770,7 @@ static void domain_read_resources(struct device *dev) pci_domain_read_resources(dev); /* TOP_MEM MSR is our boundary between DRAM and MMIO under 4G */ - mmio_basek = bsp_topmem() >> 10; + mmio_basek = amd_topmem() >> 10; #if CONFIG_HW_MEM_HOLE_SIZEK != 0 /* if the hw mem hole is already set in raminit stage, here we will compare @@ -826,7 +826,7 @@ static void domain_read_resources(struct device *dev) sizek = 0; } else { - uint64_t topmem2 = bsp_topmem2(); + uint64_t topmem2 = amd_topmem2(); basek = 4*1024*1024; sizek = topmem2/1024 - basek; } @@ -995,13 +995,6 @@ static struct device_operations cpu_bus_ops = { static void root_complex_enable_dev(struct device *dev) { - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) { dev->ops = &pci_domain_ops; diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 5cc52b6926..666deda7d4 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -131,7 +131,6 @@ static void enable_dev(struct device *dev) static void soc_init(void *chip_info) { fch_init(chip_info); - setup_bsp_ramtop(); } static void soc_final(void *chip_info) diff --git a/src/soc/amd/stoneyridge/northbridge.c b/src/soc/amd/stoneyridge/northbridge.c index d5231ad5d5..5d5ed7a38a 100644 --- a/src/soc/amd/stoneyridge/northbridge.c +++ b/src/soc/amd/stoneyridge/northbridge.c @@ -332,7 +332,7 @@ static const struct pci_driver family15_northbridge __pci_driver = { */ void amd_initcpuio(void) { - uintptr_t topmem = bsp_topmem(); + uintptr_t topmem = amd_topmem(); uintptr_t base, limit; /* Enable legacy video routing: D18F1xF4 VGA Enable */ |