diff options
| -rw-r--r-- | src/soc/nvidia/tegra210/include/soc/addressmap.h | 1 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra210/ramstage.c | 22 |
2 files changed, 23 insertions, 0 deletions
diff --git a/src/soc/nvidia/tegra210/include/soc/addressmap.h b/src/soc/nvidia/tegra210/include/soc/addressmap.h index 66888c6a69..c3af00c0b2 100644 --- a/src/soc/nvidia/tegra210/include/soc/addressmap.h +++ b/src/soc/nvidia/tegra210/include/soc/addressmap.h @@ -35,6 +35,7 @@ enum { TEGRA_ARM_PERIPHBASE = 0x50040000, TEGRA_GICD_BASE = 0x50041000, TEGRA_GICC_BASE = 0x50042000, + TEGRA_MSELECT_CONFIG = 0x50060000, TEGRA_ARM_DISPLAYA = 0x54200000, TEGRA_ARM_DISPLAYB = 0x54240000, TEGRA_DSIA_BASE = 0x54300000, diff --git a/src/soc/nvidia/tegra210/ramstage.c b/src/soc/nvidia/tegra210/ramstage.c index 7838c69ab9..f37c8179c6 100644 --- a/src/soc/nvidia/tegra210/ramstage.c +++ b/src/soc/nvidia/tegra210/ramstage.c @@ -31,8 +31,30 @@ void arm64_arch_timer_init(void) set_cntfrq(freq); } +static void mselect_enable_wrap(void) +{ + uint32_t reg; + +#define ERR_RESP_EN_SLAVE1 (0x1 << 24) +#define ERR_RESP_EN_SLAVE2 (0x1 << 25) +#define WRAP_TO_INCR_SLAVE0 (0x1 << 27) +#define WRAP_TO_INCR_SLAVE1 (0x1 << 28) +#define WRAP_TO_INCR_SLAVE2 (0x1 << 29) + + reg = read32((void *)TEGRA_MSELECT_CONFIG); + /* Disable error mechanism */ + reg &= ~(ERR_RESP_EN_SLAVE1 | ERR_RESP_EN_SLAVE2); + /* Enable WRAP type conversion */ + reg |= (WRAP_TO_INCR_SLAVE0 | WRAP_TO_INCR_SLAVE1 | + WRAP_TO_INCR_SLAVE2); + write32((void *)TEGRA_MSELECT_CONFIG, reg); +} + void arm64_soc_init(void) { + /* Enable WRAP to INCR burst type conversion in MSELECT */ + mselect_enable_wrap(); + trustzone_region_init(); tegra210_mmu_init(); |