diff options
| -rw-r--r-- | src/soc/intel/apollolake/Kconfig | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/bootblock/bootblock.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/include/soc/uart.h | 9 | ||||
| -rw-r--r-- | src/soc/intel/apollolake/uart_early.c | 37 |
4 files changed, 18 insertions, 32 deletions
diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 7ec97bf11c..dc639a237c 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -57,6 +57,8 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_RTC + select SOC_INTEL_COMMON_BLOCK_SA + select SOC_INTEL_COMMON_BLOCK_UART select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_SMI select SOC_INTEL_COMMON_SPI_FLASH_PROTECT diff --git a/src/soc/intel/apollolake/bootblock/bootblock.c b/src/soc/intel/apollolake/bootblock/bootblock.c index 62fe47b3eb..8a56890af5 100644 --- a/src/soc/intel/apollolake/bootblock/bootblock.c +++ b/src/soc/intel/apollolake/bootblock/bootblock.c @@ -145,7 +145,7 @@ void bootblock_soc_early_init(void) /* Prepare UART for serial console. */ if (IS_ENABLED(CONFIG_SOC_UART_DEBUG)) - soc_console_uart_init(); + pch_uart_init(); if (IS_ENABLED(CONFIG_TPM_ON_FAST_SPI)) tpm_enable(); diff --git a/src/soc/intel/apollolake/include/soc/uart.h b/src/soc/intel/apollolake/include/soc/uart.h index c7ba4a657a..b2b1bb8623 100644 --- a/src/soc/intel/apollolake/include/soc/uart.h +++ b/src/soc/intel/apollolake/include/soc/uart.h @@ -18,9 +18,14 @@ #ifndef _SOC_APOLLOLAKE_UART_H_ #define _SOC_APOLLOLAKE_UART_H_ -void lpss_console_uart_init(void); +/* +* M and N divisor values for clock frequency configuration. +* These values get us a 1.836 MHz clock (ideally we want 1.843 MHz) +*/ +#define CLK_M_VAL 0x025a +#define CLK_N_VAL 0x7fff /* Initialize the console UART including the pads for the configured UART. */ -void soc_console_uart_init(void); +void pch_uart_init(void); #endif /* _SOC_APOLLOLAKE_UART_H_ */ diff --git a/src/soc/intel/apollolake/uart_early.c b/src/soc/intel/apollolake/uart_early.c index 0a32b715b0..311e580636 100644 --- a/src/soc/intel/apollolake/uart_early.c +++ b/src/soc/intel/apollolake/uart_early.c @@ -17,7 +17,7 @@ #include <console/uart.h> #include <device/pci.h> -#include <intelblocks/lpss.h> +#include <intelblocks/uart.h> #include <soc/gpio.h> #include <soc/uart.h> #include <soc/pci_devs.h> @@ -31,32 +31,6 @@ static inline int invalid_uart_for_console(void) return 0; } -void lpss_console_uart_init(void) -{ - uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS; - device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3); - - if (invalid_uart_for_console()) - return; - - /* Enable BAR0 for the UART -- this is where the 8250 registers hide */ - pci_write_config32(uart, PCI_BASE_ADDRESS_0, base); - - /* Enable memory access and bus master */ - pci_write_config32(uart, PCI_COMMAND, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - - /* Take UART out of reset */ - lpss_reset_release(base); - - /* - * Set M and N divisor inputs and enable clock. These values - * get us a 1.836 MHz clock (ideally we want 1.843 MHz) - */ - lpss_clk_update(base, 0x025a, 0x7fff); - -} - uintptr_t uart_platform_base(int idx) { return CONFIG_CONSOLE_UART_BASE_ADDRESS; @@ -69,8 +43,11 @@ static const struct pad_config uart_gpios[] = { PAD_CFG_NF(GPIO_47, NATIVE, DEEP, NF1), /* UART2 TX */ }; -void soc_console_uart_init(void) +void pch_uart_init(void) { + uintptr_t base = CONFIG_CONSOLE_UART_BASE_ADDRESS; + device_t uart = _PCH_DEV(UART, CONFIG_UART_FOR_CONSOLE & 3); + /* Get a 0-based pad index. See invalid_uart_for_console() above. */ const int pad_index = CONFIG_UART_FOR_CONSOLE - 1; @@ -80,5 +57,7 @@ void soc_console_uart_init(void) /* Configure the 2 pads per UART. */ gpio_configure_pads(&uart_gpios[pad_index * 2], 2); - lpss_console_uart_init(); + /* Program UART2 BAR0, command, reset and clock register */ + uart_common_init(uart, base, CLK_M_VAL, CLK_N_VAL); + } |