diff options
| -rw-r--r-- | src/mainboard/asrock/g41c-gs/romstage.c | 39 | ||||
| -rw-r--r-- | src/mainboard/asus/p5qc/romstage.c | 46 | ||||
| -rw-r--r-- | src/mainboard/asus/p5ql-em/romstage.c | 51 | ||||
| -rw-r--r-- | src/mainboard/asus/p5qpl-am/romstage.c | 48 | ||||
| -rw-r--r-- | src/mainboard/foxconn/g41s-k/romstage.c | 49 | ||||
| -rw-r--r-- | src/mainboard/gigabyte/ga-g41m-es2l/romstage.c | 48 | ||||
| -rw-r--r-- | src/mainboard/intel/dg41wv/romstage.c | 42 | ||||
| -rw-r--r-- | src/mainboard/intel/dg43gt/romstage.c | 46 | ||||
| -rw-r--r-- | src/mainboard/lenovo/thinkcentre_a58/romstage.c | 39 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/romstage.c | 71 | ||||
| -rw-r--r-- | src/northbridge/intel/x4x/x4x.h | 3 |
12 files changed, 150 insertions, 333 deletions
diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/romstage.c index b054897509..06e13eb652 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/romstage.c @@ -16,11 +16,7 @@ */ #include <device/pnp_ops.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <arch/romstage.h> #include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/nuvoton/common/nuvoton.h> #include <superio/nuvoton/nct6776/nct6776.h> @@ -30,9 +26,8 @@ #define SERIAL_DEV_R2 PNP_DEV(0x2e, NCT6776_SP1) #define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1) #define SUPERIO_DEV PNP_DEV(0x2e, 0) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) -static void mb_lpc_setup(void) +void mb_lpc_setup(void) { /* Set GPIOs on superio, enable UART */ if (CONFIG(SUPERIO_NUVOTON_NCT6776)) { @@ -53,34 +48,8 @@ static void mb_lpc_setup(void) RCBA16(D29IR) = 0x0237; } -void mainboard_romstage_entry(void) +void mb_get_spd_map(u8 spd_map[4]) { - // ch0 ch1 - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801gx_lpc_setup(); - mb_lpc_setup(); - - console_init(); - - enable_smbus(); - - i82801gx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); - + spd_map[0] = 0x50; + spd_map[2] = 0x52; } diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/romstage.c index 9a90f74189..53aa176b38 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/romstage.c @@ -14,57 +14,27 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> -#include <console/console.h> #include <southbridge/intel/i82801jx/i82801jx.h> -#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <arch/romstage.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> #include <superio/winbond/common/winbond.h> #define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) -/* Early mainboard specific GPIO setup. - * We should use standard gpio.h eventually - */ - -static void mb_misc_rcba(void) +void mb_lpc_setup(void) { /* TODO? */ RCBA32(RCBA_CG) = 0xbf7f001f; RCBA32(0x3430) = 0x00000002; RCBA32(0x3f00) = 0x00000038; -} -void mainboard_romstage_entry(void) -{ - const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801jx_lpc_setup(); - mb_misc_rcba(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} - console_init(); - - enable_smbus(); - - i82801jx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[1] = 0x51; + spd_map[2] = 0x52; + spd_map[3] = 0x53; } diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/romstage.c index c7ade1c541..fa22a645d4 100644 --- a/src/mainboard/asus/p5ql-em/romstage.c +++ b/src/mainboard/asus/p5ql-em/romstage.c @@ -12,22 +12,22 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> #include <device/pnp_ops.h> #include <console/console.h> -#include <southbridge/intel/i82801jx/i82801jx.h> -#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> #include <cpu/x86/msr.h> #include <cpu/intel/speedstep.h> -#include <arch/romstage.h> #include <cf9_reset.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/common/winbond.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +void mb_lpc_setup(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} static u8 msr_get_fsb(void) { @@ -103,41 +103,20 @@ static int setup_sio_gpio(void) return need_reset; } -void mainboard_romstage_entry(void) +void mb_pre_raminit_setup(int s3_resume) { - /* This board has first dimm slot of each channel hooked up to - rank0 and rank1, while the second dimm slot is only connected - to rank1. The raminit does not support such setups - const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; */ - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801jx_lpc_setup(); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - enable_smbus(); - - i82801jx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - if (!s3_resume && setup_sio_gpio()) { printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); full_reset(); } +} - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); +void mb_get_spd_map(u8 spd_map[4]) +{ + /* This board has first dimm slot of each channel hooked up to + rank0 and rank1, while the second dimm slot is only connected + to rank1. The raminit does not support such setups. So only the + first dimms of each channel are used. */ + spd_map[0] = 0x50; + spd_map[2] = 0x52; } diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/romstage.c index de3972db4e..ad16c0f72a 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/romstage.c @@ -17,20 +17,20 @@ #include <cf9_reset.h> #include <device/pnp_ops.h> -#include <device/pci_ops.h> #include <console/console.h> -#include <arch/romstage.h> #include <cpu/intel/speedstep.h> #include <cpu/x86/msr.h> #include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/common/pmclib.h> -#include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) + +void mb_lpc_setup(void) +{ + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} static u8 msr_get_fsb(void) { @@ -127,40 +127,16 @@ static int setup_sio_gpio(void) return need_reset; } -void mainboard_romstage_entry(void) +void mb_pre_raminit_setup(int s3_resume) { - // ch0 ch1 - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801gx_lpc_setup(); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - enable_smbus(); - - i82801gx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - if (!s3_resume && setup_sio_gpio()) { - printk(BIOS_DEBUG, - "Needs reset to configure CPU BSEL straps\n"); + printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n"); full_reset(); } +} - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); - +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x52; } diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/romstage.c index 45ff7e458e..b4bd77d78b 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/romstage.c @@ -16,20 +16,15 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <arch/romstage.h> -#include <device/pci_ops.h> #include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8720f/it8720f.h> -#define LPC_DEV PCI_DEV(0, 0x1f, 0) #define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO) -static void mb_lpc_setup(void) +void mb_lpc_setup(void) { /* Set up GPIOs on Super I/O. */ ite_reg_write(GPIO_DEV, 0x25, 0x01); @@ -55,43 +50,13 @@ static void mb_lpc_setup(void) RCBA16(D29IR) = 0x0237; RCBA32(FD) |= FD_INTLAN; -} - -void mainboard_romstage_entry(void) -{ - // ch0 ch1 -#if CONFIG(BOARD_FOXCONN_G41S_K) - const u8 spd_addrmap[4] = { 0x50, 0, 0, 0 }; -#else - /* TODO adapt raminit such that other slots can be used - * for single rank dimms */ - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; -#endif - u8 boot_path = 0; - u8 s3_resume; - /* Set up southbridge and Super I/O GPIOs. */ - i82801gx_lpc_setup(); - mb_lpc_setup(); ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} - console_init(); - - enable_smbus(); - - i82801gx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); - +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + if (CONFIG(BOARD_FOXCONN_G41M)) + spd_map[2] = 0x52; } diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c index 16b157b2dd..bde4f33bef 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c @@ -14,14 +14,9 @@ * GNU General Public License for more details. */ -#include <stdint.h> -#include <device/pci_def.h> #include <device/pci_ops.h> -#include <console/console.h> #include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <arch/romstage.h> #include <superio/ite/it8718f/it8718f.h> #include <superio/ite/common/ite.h> @@ -34,7 +29,7 @@ * We should use standard gpio.h eventually */ -static void mb_lpc_init(void) +void mb_lpc_setup(void) { pci_devfn_t dev; @@ -73,6 +68,11 @@ static void mb_lpc_init(void) ite_reg_write(EC_DEV, 0x70, 0x00); // Don't use IRQ9 ite_reg_write(EC_DEV, 0x30, 0x01); // Enable + ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + /* Disable SIO reboot */ + ite_reg_write(GPIO_DEV, 0xEF, 0x7E); + /* IRQ routing */ RCBA32(D31IP) = 0x00002210; RCBA32(D30IP) = 0x00002100; @@ -84,38 +84,8 @@ static void mb_lpc_init(void) RCBA32(D27IR) = 0x00000000; } -void mainboard_romstage_entry(void) +void mb_get_spd_map(u8 spd_map[4]) { - // ch0 ch1 - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801gx_lpc_setup(); - mb_lpc_init(); - ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - /* Disable SIO reboot */ - ite_reg_write(GPIO_DEV, 0xEF, 0x7E); - - console_init(); - - enable_smbus(); - - i82801gx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); - + spd_map[0] = 0x50; + spd_map[2] = 0x52; } diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/romstage.c index 0d7c162272..ff018af5f6 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/romstage.c @@ -16,19 +16,14 @@ */ #include <device/pnp_ops.h> -#include <device/pci_ops.h> -#include <console/console.h> -#include <arch/romstage.h> #include <northbridge/intel/x4x/x4x.h> -#include <southbridge/intel/common/pmclib.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) -static void mb_lpc_setup(void) +void mb_lpc_setup(void) { /* Set GPIOs on superio, enable UART */ pnp_enter_ext_func_mode(SERIAL_DEV); @@ -38,40 +33,15 @@ static void mb_lpc_setup(void) pnp_exit_ext_func_mode(SERIAL_DEV); + winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + /* IRQ routing */ RCBA16(D31IR) = 0x0132; RCBA16(D29IR) = 0x0237; } -void mainboard_romstage_entry(void) +void mb_get_spd_map(u8 spd_map[4]) { - // ch0 ch1 - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801gx_lpc_setup(); - mb_lpc_setup(); - winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - - console_init(); - - enable_smbus(); - - i82801gx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); - + spd_map[0] = 0x50; + spd_map[2] = 0x52; } diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/romstage.c index b851f98627..71fd87ad74 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/romstage.c @@ -14,23 +14,14 @@ * GNU General Public License for more details. */ -#include <device/pci_ops.h> -#include <console/console.h> #include <southbridge/intel/i82801jx/i82801jx.h> -#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <arch/romstage.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <superio/winbond/common/winbond.h> #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) -/* Early mainboard specific GPIO setup. - * We should use standard gpio.h eventually - */ - -static void mb_misc_rcba(void) +void mb_lpc_setup(void) { RCBA32(0x3410) = 0x00060464; RCBA32(RCBA_BUC) &= ~BUC_LAND; @@ -38,35 +29,14 @@ static void mb_misc_rcba(void) RCBA32(0x341c) = 0xbf7f001f; RCBA32(0x3430) = 0x00000002; RCBA32(0x3f00) = 0x0000000b; -} -void mainboard_romstage_entry(void) -{ - const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801jx_lpc_setup(); - mb_misc_rcba(); winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} - console_init(); - - enable_smbus(); - - i82801jx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[1] = 0x51; + spd_map[2] = 0x52; + spd_map[3] = 0x53; } diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/romstage.c index 8be2c86734..5594cbdda6 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/romstage.c @@ -15,45 +15,18 @@ * GNU General Public License for more details. */ -#include <console/console.h> -#include <southbridge/intel/i82801gx/i82801gx.h> -#include <southbridge/intel/common/pmclib.h> #include <northbridge/intel/x4x/x4x.h> -#include <arch/romstage.h> -#include <device/pci_ops.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -#define LPC_DEV PCI_DEV(0, 0x1f, 0) -void mainboard_romstage_entry(void) +void mb_lpc_setup(void) { - // ch0 ch1 - const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 }; - u8 boot_path = 0; - u8 s3_resume; - - /* Set southbridge and Super I/O GPIOs. */ - i82801gx_lpc_setup(); smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); +} - console_init(); - - enable_smbus(); - - i82801gx_early_init(); - x4x_early_init(); - - s3_resume = southbridge_detect_s3_resume(); - if (s3_resume) - boot_path = BOOT_PATH_RESUME; - if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) - boot_path = BOOT_PATH_WARM_RESET; - - sdram_initialize(boot_path, spd_addrmap); - - x4x_late_init(s3_resume); - - printk(BIOS_DEBUG, "x4x late init complete\n"); - +void mb_get_spd_map(u8 spd_map[4]) +{ + spd_map[0] = 0x50; + spd_map[2] = 0x52; } diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index b7fd2fe7ae..79a03cb77e 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -23,6 +23,7 @@ romstage-y += memmap.c romstage-y += rcven.c romstage-y += raminit_tables.c romstage-y += dq_dqs.c +romstage-y += romstage.c ramstage-y += acpi.c ramstage-y += memmap.c diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c new file mode 100644 index 0000000000..c3a503643f --- /dev/null +++ b/src/northbridge/intel/x4x/romstage.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/pci_ops.h> +#include <console/console.h> +#include <southbridge/intel/common/pmclib.h> +#include <northbridge/intel/x4x/x4x.h> +#include <arch/romstage.h> + +#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) +#include <southbridge/intel/i82801jx/i82801jx.h> +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) +#include <southbridge/intel/i82801gx/i82801gx.h> +#endif + +__weak void mb_pre_raminit_setup(int s3_resume) +{ +} + +void mainboard_romstage_entry(void) +{ + u8 spd_addr_map[4] = {}; + u8 boot_path = 0; + u8 s3_resume; + +#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) + i82801jx_lpc_setup(); +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) + i82801gx_lpc_setup(); +#endif + + mb_lpc_setup(); + + console_init(); + + enable_smbus(); + +#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) + i82801jx_early_init(); +#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) + i82801gx_early_init(); +#endif + + x4x_early_init(); + + s3_resume = southbridge_detect_s3_resume(); + mb_pre_raminit_setup(s3_resume); + + if (s3_resume) + boot_path = BOOT_PATH_RESUME; + if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET) + boot_path = BOOT_PATH_WARM_RESET; + + mb_get_spd_map(spd_addr_map); + sdram_initialize(boot_path, spd_addr_map); + + x4x_late_init(s3_resume); + + printk(BIOS_DEBUG, "x4x late init complete\n"); +} diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 76e82d9494..e4a6c215d8 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -373,6 +373,9 @@ enum ddr2_signals { void x4x_early_init(void); void x4x_late_init(int s3resume); +void mb_lpc_setup(void); +void mb_get_spd_map(u8 spd_map[4]); +void mb_pre_raminit_setup(int s3_resume); u32 decode_igd_memory_size(u32 gms); u32 decode_igd_gtt_size(u32 gsm); u32 decode_tseg_size(const u32 esmramc); |