diff options
| -rw-r--r-- | src/soc/intel/xeon_sp/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/ramstage.c | 26 |
2 files changed, 27 insertions, 1 deletions
diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 8a26c14acc..ffc55b6d4a 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -7,7 +7,7 @@ subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c pmutil.c -ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c +ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c nb_acpi.c ramstage.c ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC) += pmc.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/ramstage.c b/src/soc/intel/xeon_sp/ramstage.c new file mode 100644 index 0000000000..68d5d4658c --- /dev/null +++ b/src/soc/intel/xeon_sp/ramstage.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <smbios.h> + +unsigned int smbios_cache_error_correction_type(u8 level) +{ + return SMBIOS_CACHE_ERROR_CORRECTION_SINGLE_BIT; +} + +unsigned int smbios_cache_sram_type(void) +{ + return SMBIOS_CACHE_SRAM_TYPE_SYNCHRONOUS; +} + +unsigned int smbios_cache_conf_operation_mode(u8 level) +{ + switch (level) { + case 1: + return SMBIOS_CACHE_OP_MODE_WRITE_BACK; + case 2: + case 3: + return SMBIOS_CACHE_OP_MODE_VARIES_WITH_MEMORY_ADDRESS; + default: + return SMBIOS_CACHE_OP_MODE_UNKNOWN; + } +} |