diff options
| -rw-r--r-- | src/soc/intel/alderlake/romstage/fsp_params.c | 54 | ||||
| -rw-r--r-- | src/soc/intel/alderlake/romstage/romstage.c | 6 |
2 files changed, 45 insertions, 15 deletions
diff --git a/src/soc/intel/alderlake/romstage/fsp_params.c b/src/soc/intel/alderlake/romstage/fsp_params.c index b5e54f82a6..d4608eee26 100644 --- a/src/soc/intel/alderlake/romstage/fsp_params.c +++ b/src/soc/intel/alderlake/romstage/fsp_params.c @@ -13,6 +13,7 @@ #include <gpio.h> #include <intelbasecode/debug_feature.h> #include <intelblocks/cpulib.h> +#include <intelblocks/cse.h> #include <intelblocks/pcie_rp.h> #include <option.h> #include <soc/iomap.h> @@ -411,6 +412,47 @@ static void debug_override_memory_init_params(FSP_M_CONFIG *mupd) debug_get_pch_cpu_tracehub_modes(&mupd->CpuTraceHubMode, &mupd->PchTraceHubMode); } +static void fill_fspm_sign_of_life(FSP_M_CONFIG *m_cfg, + FSPM_ARCH_UPD *arch_upd) +{ + const char *name; + bool esol_required = false; + + /* + * Memory training + * + * If valid MRC cache data is not found, FSP should perform a memory + * training. Memory training can take a while so let's inform the end + * user with an on-screen text message. + */ + if (!arch_upd->NvsBufferPtr) { + esol_required = true; + name = "memory training"; + elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC); + } + + /* + * CSE Sync + * + * If currently running CSE RW firmware version is different than CSE version + * packed as part of the CBFS then CSE sync will be triggered. CSE sync can take + * < 1-minute hence, let's inform the end user with an on-screen text message. + */ + if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) { + if (esol_required) { + name = "memory training and CSE update"; + } else { + name = "CSE update"; + esol_required = true; + } + + elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC); + } + + if (esol_required) + ux_inform_user_of_update_operation(name); +} + void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) { const struct soc_intel_alderlake_config *config; @@ -434,15 +476,9 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version) } } - /* - * If valid MRC cache data is not found, FSP should perform a memory - * training. Memory training can take a while so let's inform the end - * user with an on-screen text message. - */ - if (!arch_upd->NvsBufferPtr) { - if (ux_inform_user_of_update_operation("memory training")) - elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_MRC); - } + if (CONFIG(CHROMEOS_ENABLE_ESOL)) + fill_fspm_sign_of_life(m_cfg, arch_upd); + config = config_of_soc(); soc_memory_init_params(m_cfg, config); diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index f0c039ee6c..b577e32a48 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -150,12 +150,6 @@ static void save_dimm_info(void) printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } -void cse_fw_update_misc_oper(void) -{ - if (ux_inform_user_of_update_operation("CSE update")) - elog_add_event_byte(ELOG_TYPE_FW_EARLY_SOL, ELOG_FW_EARLY_SOL_CSE_SYNC); -} - void cse_board_reset(void) { early_graphics_stop(); |