diff options
| -rw-r--r-- | src/mainboard/google/rex/Kconfig | 1 | ||||
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/gpio.c | 6 | ||||
| -rw-r--r-- | src/mainboard/google/rex/variants/rex0/overridetree.cb | 16 |
3 files changed, 21 insertions, 2 deletions
diff --git a/src/mainboard/google/rex/Kconfig b/src/mainboard/google/rex/Kconfig index ebdc2aacfd..05b47479fb 100644 --- a/src/mainboard/google/rex/Kconfig +++ b/src/mainboard/google/rex/Kconfig @@ -8,6 +8,7 @@ config BOARD_GOOGLE_REX_COMMON select DRIVERS_SOUNDWIRE_ALC5682 select DRIVERS_WIFI_GENERIC select DRIVERS_INTEL_MIPI_CAMERA + select DRIVERS_SPI_ACPI select EC_GOOGLE_CHROMEEC select EC_GOOGLE_CHROMEEC_BOARDID select EC_GOOGLE_CHROMEEC_ESPI diff --git a/src/mainboard/google/rex/variants/rex0/gpio.c b/src/mainboard/google/rex/variants/rex0/gpio.c index 541402c372..c90c0c11f9 100644 --- a/src/mainboard/google/rex/variants/rex0/gpio.c +++ b/src/mainboard/google/rex/variants/rex0/gpio.c @@ -432,8 +432,12 @@ static const struct pad_config default_early_gpio_table[] = { }; static const struct pad_config romstage_gpio_table_id0[] = { - /* A20 : [] ==> SSD_PERST_L */ + /* GPP_B11 : [] ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_B11, 0, DEEP), + /* A20 : [] ==> SSD_PERST_L */ PAD_CFG_GPO(GPP_A20, 0, DEEP), + /* GPP_C23 : [] ==> FP_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 0, DEEP), /* GPP_E07 : [] ==> WWAN_FCPO_L */ PAD_CFG_GPO(GPP_E07, 1, DEEP), }; diff --git a/src/mainboard/google/rex/variants/rex0/overridetree.cb b/src/mainboard/google/rex/variants/rex0/overridetree.cb index 00cbe8c5b8..a7f5a95c32 100644 --- a/src/mainboard/google/rex/variants/rex0/overridetree.cb +++ b/src/mainboard/google/rex/variants/rex0/overridetree.cb @@ -471,7 +471,21 @@ chip soc/intel/meteorlake device generic 0 on end end end #PCIE6 WWAN card - device ref gspi1 on end + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E10_IRQ)" + register "wake" = "GPE0_DW1_10" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C23)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B11)" + register "enable_delay_ms" = "3" + device spi 0 on end + end # FPMCU + end device ref soc_espi on chip ec/google/chromeec use conn0 as mux_conn[0] |