diff options
| -rw-r--r-- | src/drivers/intel/fsp1_1/Makefile.inc | 3 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/bootblock.c | 53 | ||||
| -rw-r--r-- | src/drivers/intel/fsp1_1/include/fsp/bootblock.h | 21 | ||||
| -rw-r--r-- | src/soc/intel/skylake/bootblock/bootblock.c | 13 |
4 files changed, 85 insertions, 5 deletions
diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 011df679f4..397bad89b2 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -20,6 +20,9 @@ verstage-y += car.c verstage-y += fsp_util.c verstage-y += verstage.c +bootblock-y += bootblock.c +bootblock-y += fsp_util.c + romstage-y += car.c romstage-y += fsp_util.c romstage-y += hob.c diff --git a/src/drivers/intel/fsp1_1/bootblock.c b/src/drivers/intel/fsp1_1/bootblock.c new file mode 100644 index 0000000000..c0f26d9a72 --- /dev/null +++ b/src/drivers/intel/fsp1_1/bootblock.c @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <fsp/bootblock.h> +#include <fsp/util.h> + +static void fill_temp_ram_init_params(FSP_TEMP_RAM_INIT_PARAMS *params) +{ + params->MicrocodeRegionBase = CONFIG_CPU_MICROCODE_CBFS_LOC; + params->MicrocodeRegionLength = CONFIG_CPU_MICROCODE_CBFS_LEN; + params->CodeRegionBase = 0xFFFFFFFF - CONFIG_ROM_SIZE + 1; + params->CodeRegionLength = CONFIG_ROM_SIZE; +} + +void bootblock_fsp_temp_ram_init(void) +{ + FSP_TEMP_RAM_INIT fsp_temp_ram_init; + FSP_TEMP_RAM_INIT_PARAMS temp_ram_init_params; + FSP_INFO_HEADER *fih; + EFI_STATUS status; + + /* Locate the FSP header */ + fih = find_fsp(CONFIG_FSP_LOC); + /* Check the FSP header */ + if (fih == NULL) + die("FSP_INFO_HEADER not set!\n"); + + fill_temp_ram_init_params(&temp_ram_init_params); + + /* Perform Temp RAM Init */ + printk(BIOS_DEBUG, "Calling FspTempRamInit\n"); + post_code(POST_FSP_TEMP_RAM_INIT); + fsp_temp_ram_init = (FSP_TEMP_RAM_INIT)(fih->ImageBase + + fih->TempRamInitEntryOffset); + status = fsp_temp_ram_init(&temp_ram_init_params); + if (status != FSP_SUCCESS) + die("FspTempRamInit failed. Giving up."); + + printk(BIOS_DEBUG, "FspTempRamInit returned 0x%08x\n", status); +} diff --git a/src/drivers/intel/fsp1_1/include/fsp/bootblock.h b/src/drivers/intel/fsp1_1/include/fsp/bootblock.h new file mode 100644 index 0000000000..a962bdf0be --- /dev/null +++ b/src/drivers/intel/fsp1_1/include/fsp/bootblock.h @@ -0,0 +1,21 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef FSP1_1_BOOTBLOCK_H +#define FSP1_1_BOOTBLOCK_H + +void bootblock_fsp_temp_ram_init(void); + +#endif diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 028bb7b314..ab1720c83a 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -14,6 +14,7 @@ */ #include <bootblock_common.h> +#include <fsp/bootblock.h> #include <soc/bootblock.h> #include <soc/romstage.h> @@ -33,13 +34,15 @@ void bootblock_soc_early_init(void) pch_uart_init(); } -/* - * Perform early chipset initialization before fsp memory init - * example: pirq->irq programming, enabling smbus, pmcbase, abase, - * get platform info, i2c programming - */ void bootblock_soc_init(void) { + /* locate and call FspTempRamInit */ + bootblock_fsp_temp_ram_init(); + /* + * Perform early chipset initialization before fsp memory init + * example: pirq->irq programming, enabling smbus, pmcbase, abase, + * get platform info, i2c programming + */ report_platform_info(); set_max_freq(); pch_early_init(); |