diff options
| -rw-r--r-- | src/include/types.h | 7 | ||||
| -rw-r--r-- | src/soc/nvidia/tegra/dc.h | 1 | ||||
| -rw-r--r-- | src/soc/qualcomm/ipq806x/clock.c | 1 | ||||
| -rw-r--r-- | src/soc/qualcomm/ipq806x/include/clock.h | 1 |
4 files changed, 8 insertions, 2 deletions
diff --git a/src/include/types.h b/src/include/types.h index ef5edc1781..24ebfafc54 100644 --- a/src/include/types.h +++ b/src/include/types.h @@ -22,6 +22,13 @@ #include <stdint.h> #include <stddef.h> +/* + * This may mean something else on architectures where the bits are numbered + * from the MSB (e.g. PowerPC), but until we cross that bridge, this macro is + * perfectly fine. + */ +#define BIT(x) (1ul << (x)) + /** * Coreboot error codes * diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index c0b1986c4f..ff36a0b589 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -367,7 +367,6 @@ struct display_controller { }; check_member(display_controller, winbuf, 0x800 * 4); -#define BIT(pos) (1U << pos) /* DC_CMD_DISPLAY_COMMAND 0x032 */ #define DISP_COMMAND_RAISE (1 << 0) diff --git a/src/soc/qualcomm/ipq806x/clock.c b/src/soc/qualcomm/ipq806x/clock.c index 88056d4923..ee2ed64ffb 100644 --- a/src/soc/qualcomm/ipq806x/clock.c +++ b/src/soc/qualcomm/ipq806x/clock.c @@ -3,6 +3,7 @@ */ #include <delay.h> +#include <types.h> #include <clock.h> /** diff --git a/src/soc/qualcomm/ipq806x/include/clock.h b/src/soc/qualcomm/ipq806x/include/clock.h index 98f6661e02..d9e783479c 100644 --- a/src/soc/qualcomm/ipq806x/include/clock.h +++ b/src/soc/qualcomm/ipq806x/include/clock.h @@ -40,7 +40,6 @@ /* UART specific definitions */ -#define BIT(s) (1<<s) #define Uart_ns_val NS(BIT_POS_31,BIT_POS_16,N_VALUE,M_VALUE, 5, 4, 3, 1, 2, 0,3) #define Uart_clk_ns_mask (BM(BIT_POS_31, BIT_POS_16) | BM(BIT_POS_6, BIT_POS_0)) #define Uart_mnd_en_mask BIT(8) * !!(625) |