diff options
| -rw-r--r-- | src/northbridge/intel/x4x/bootblock.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index 80375a75ff..71a0609e55 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -21,7 +21,7 @@ static uint32_t encode_pciexbar_length(void) void bootblock_early_northbridge_init(void) { /* Disable LaGrande Technology (LT) */ - read32((void *)TPM_BASE_ADDRESS); + read32p(TPM_BASE_ADDRESS); const uint32_t reg32 = CONFIG_ECAM_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1; pci_io_write_config32(HOST_BRIDGE, D0F0_PCIEXBAR_LO, reg32); |