diff options
| -rw-r--r-- | src/mainboard/google/slippy/devicetree.cb | 4 | ||||
| -rw-r--r-- | src/southbridge/intel/lynxpoint/early_pch.c | 2 |
2 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/google/slippy/devicetree.cb b/src/mainboard/google/slippy/devicetree.cb index 8cf387fff8..5fb3cb4c1b 100644 --- a/src/mainboard/google/slippy/devicetree.cb +++ b/src/mainboard/google/slippy/devicetree.cb @@ -41,6 +41,10 @@ chip northbridge/intel/haswell register "pirqg_routing" = "0x80" register "pirqh_routing" = "0x80" + # EC range is 0x800-0x9ff + register "gen1_dec" = "0x00fc0801" + register "gen2_dec" = "0x00fc0901" + register "alt_gp_smi_en" = "0x0000" register "gpe0_en_1" = "0x00000000" # EC_SCI is GPIO36 diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 1a78d571e6..7a24e1fb03 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -102,7 +102,7 @@ static void pch_enable_lpc(void) pci_write_config16(dev, LPC_IO_DEC, 0x0010); /* Enable SuperIO + MC + COM1 + PS/2 Keyboard/Mouse */ - u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | + u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | GAMEL_LPC_EN | COMA_LPC_EN | KBC_LPC_EN | MC_LPC_EN; pci_write_config16(dev, LPC_EN, lpc_config); } |