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-rw-r--r--src/mainboard/google/gru/bootblock.c4
-rw-r--r--src/mainboard/google/gru/chromeos.c24
-rw-r--r--src/soc/rockchip/rk3399/Makefile.inc2
3 files changed, 25 insertions, 5 deletions
diff --git a/src/mainboard/google/gru/bootblock.c b/src/mainboard/google/gru/bootblock.c
index 1166d8a842..a048188e0a 100644
--- a/src/mainboard/google/gru/bootblock.c
+++ b/src/mainboard/google/gru/bootblock.c
@@ -21,6 +21,8 @@
#include <soc/spi.h>
#include <console/console.h>
+#include "board.h"
+
void bootblock_mainboard_early_init(void)
{
/* Let gpio2ab io domains works at 1.8V.
@@ -62,4 +64,6 @@ void bootblock_mainboard_init(void)
write32(&rk3399_pmugrf->spi1_csclktx, IOMUX_SPI1_CSCLKTX);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 24750*KHz);
+
+ setup_chromeos_gpios();
}
diff --git a/src/mainboard/google/gru/chromeos.c b/src/mainboard/google/gru/chromeos.c
index da57d861c6..4265f8d9c1 100644
--- a/src/mainboard/google/gru/chromeos.c
+++ b/src/mainboard/google/gru/chromeos.c
@@ -15,15 +15,22 @@
*/
#include <boot/coreboot_tables.h>
+#include <gpio.h>
#include <vendorcode/google/chromeos/chromeos.h>
+#include "board.h"
+
void fill_lb_gpios(struct lb_gpios *gpios)
{
-}
+ struct lb_gpio chromeos_gpios[] = {
+ {GPIO_WP.raw, ACTIVE_LOW, gpio_get(GPIO_WP), "write protect"},
+ {GPIO_BACKLIGHT.raw, ACTIVE_HIGH, -1, "backlight"},
+ {GPIO_EC_IN_RW.raw, ACTIVE_HIGH, -1, "EC in RW"},
+ {GPIO_EC_IRQ.raw, ACTIVE_LOW, -1, "EC interrupt"},
+ {GPIO_RESET.raw, ACTIVE_HIGH, -1, "reset"},
+ };
-int get_developer_mode_switch(void)
-{
- return 0;
+ lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
int get_recovery_mode_switch(void)
@@ -33,5 +40,12 @@ int get_recovery_mode_switch(void)
int get_write_protect_state(void)
{
- return 0;
+ return !gpio_get(GPIO_WP);
+}
+
+void setup_chromeos_gpios(void)
+{
+ gpio_input(GPIO_WP);
+ gpio_input_pullup(GPIO_EC_IN_RW);
+ gpio_input_pullup(GPIO_EC_IRQ);
}
diff --git a/src/soc/rockchip/rk3399/Makefile.inc b/src/soc/rockchip/rk3399/Makefile.inc
index 8abafe362b..77958d577f 100644
--- a/src/soc/rockchip/rk3399/Makefile.inc
+++ b/src/soc/rockchip/rk3399/Makefile.inc
@@ -47,6 +47,8 @@ romstage-y += ../common/pwm.c
romstage-y += timer.c
romstage-y += romstage.c
romstage-y += tsadc.c
+romstage-y += gpio.c
+romstage-y += ../common/gpio.c
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