diff options
| -rw-r--r-- | src/soc/amd/cezanne/chip.h | 2 | ||||
| -rw-r--r-- | src/soc/amd/cezanne/root_complex.c | 8 |
2 files changed, 3 insertions, 7 deletions
diff --git a/src/soc/amd/cezanne/chip.h b/src/soc/amd/cezanne/chip.h index b22590a021..00eb560b64 100644 --- a/src/soc/amd/cezanne/chip.h +++ b/src/soc/amd/cezanne/chip.h @@ -86,8 +86,6 @@ struct soc_amd_cezanne_config { uint32_t telemetry_vddcrsocfull_scale_current_mA; uint32_t telemetry_vddcrsocoffset; - bool dptc_enable; - /* The array index is the general purpose PCIe clock output number. Values in here aren't the values written to the register to have the default to be always on. */ enum gpp_clk_req gpp_clk_config[GPP_CLK_OUTPUT_COUNT]; diff --git a/src/soc/amd/cezanne/root_complex.c b/src/soc/amd/cezanne/root_complex.c index 77a94f52d7..8ea5c9fb29 100644 --- a/src/soc/amd/cezanne/root_complex.c +++ b/src/soc/amd/cezanne/root_complex.c @@ -186,10 +186,7 @@ static void acipgen_dptci(void) { const struct soc_amd_cezanne_config *config = config_of_soc(); - if (!config->dptc_enable) - return; - - /* DPTC is enabled. Always fill out the default DPTC values. */ + /* Normal mode DPTC values. */ struct dptc_input default_input = DPTC_INPUTS(config->thermctl_limit_degreeC, config->sustained_power_limit_mW, config->fast_ppt_limit_mW, @@ -200,7 +197,8 @@ static void acipgen_dptci(void) static void root_complex_fill_ssdt(const struct device *device) { acpi_fill_root_complex_tom(device); - acipgen_dptci(); + if (CONFIG(SOC_AMD_COMMON_BLOCK_ACPI_DPTC)) + acipgen_dptci(); } static const char *gnb_acpi_name(const struct device *dev) |