diff options
| -rw-r--r-- | src/southbridge/intel/bd82x6x/Makefile.inc | 8 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/me.c | 23 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/me.h | 5 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/me_8.x.c | 8 |
4 files changed, 29 insertions, 15 deletions
diff --git a/src/southbridge/intel/bd82x6x/Makefile.inc b/src/southbridge/intel/bd82x6x/Makefile.inc index f086426aa5..11a6b08081 100644 --- a/src/southbridge/intel/bd82x6x/Makefile.inc +++ b/src/southbridge/intel/bd82x6x/Makefile.inc @@ -17,9 +17,6 @@ ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA ## -me-src-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += me.c -me-src-$(CONFIG_NORTHBRIDGE_INTEL_IVYBRIDGE) += me_8.x.c - driver-y += pch.c driver-y += azalia.c driver-y += lpc.c @@ -27,7 +24,8 @@ driver-y += pci.c driver-y += pcie.c driver-y += sata.c driver-y += usb_ehci.c -driver-y += $(me-src-y) +driver-y += me.c +driver-y += me_8.x.c driver-y += smbus.c ramstage-y += me_status.c @@ -37,7 +35,7 @@ ramstage-y += watchdog.c ramstage-y += spi.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c -smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c $(me-src-y) finalize.c +smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me.c me_8.x.c finalize.c romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c romstage-$(CONFIG_USBDEBUG) += usb_debug.c diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 1b7b2623c2..0c40ab4276 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -353,8 +353,9 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, return 0; } +#ifdef __SMM__ /* Send END OF POST message to the ME */ -int mkhi_end_of_post(void) +static int mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -376,6 +377,7 @@ int mkhi_end_of_post(void) printk(BIOS_INFO, "ME: END OF POST message successful\n"); return 0; } +#endif #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) && !defined(__SMM__) /* Get ME firmware version */ @@ -460,6 +462,7 @@ static int mkhi_get_fwcaps(void) } #endif +#if CONFIG_CHROMEOS && 0 /* DISABLED */ /* Tell ME to issue a global reset */ int mkhi_global_reset(void) { @@ -490,10 +493,10 @@ int mkhi_global_reset(void) printk(BIOS_ERR, "ME: Global Reset failed\n"); return -1; } +#endif #ifdef __SMM__ - -void intel_me_finalize_smm(void) +static void intel_me7_finalize_smm(void) { struct me_hfs hfs; u32 reg32; @@ -528,6 +531,20 @@ void intel_me_finalize_smm(void) RCBA32_OR(FD2, PCH_DISABLE_MEI1); } +void intel_me_finalize_smm(void) +{ + u32 did = pci_read_config32(PCH_ME_DEV, PCI_VENDOR_ID); + switch (did) { + case 0x80861c3a: + intel_me7_finalize_smm(); + break; + case 0x80861e3a: + intel_me8_finalize_smm(); + break; + default: + printk(BIOS_ERR, "No finalize handler for ME %08x.\n", did); + } +} #else /* !__SMM__ */ /* Determine the path that we should take based on ME status */ diff --git a/src/southbridge/intel/bd82x6x/me.h b/src/southbridge/intel/bd82x6x/me.h index 53964a2faa..aaeb24d65d 100644 --- a/src/southbridge/intel/bd82x6x/me.h +++ b/src/southbridge/intel/bd82x6x/me.h @@ -248,14 +248,11 @@ void intel_early_me_status(void); int intel_early_me_init(void); int intel_early_me_uma_size(void); int intel_early_me_init_done(u8 status); -#else -/* ME Kernel Host Interface Messages */ -int mkhi_end_of_post(void); -int mkhi_global_reset(void); #endif #ifdef __SMM__ void intel_me_finalize_smm(void); +void intel_me8_finalize_smm(void); #endif typedef struct { u32 major_version : 16; diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index c7a69fe5c4..32f660efbc 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -357,7 +357,7 @@ static inline int mei_sendrecv(struct mei_header *mei, struct mkhi_header *mkhi, } /* Send END OF POST message to the ME */ -int mkhi_end_of_post(void) +static int mkhi_end_of_post(void) { struct mkhi_header mkhi = { .group_id = MKHI_GROUP_ID_GEN, @@ -457,8 +457,9 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section) } #endif +#if CONFIG_CHROMEOS && 0 /* DISABLED */ /* Tell ME to issue a global reset */ -int mkhi_global_reset(void) +static int mkhi_global_reset(void) { struct me_global_reset reset = { .request_origin = GLOBAL_RESET_BIOS_POST, @@ -486,10 +487,11 @@ int mkhi_global_reset(void) printk(BIOS_ERR, "ME: Global Reset failed\n"); return -1; } +#endif #ifdef __SMM__ -void intel_me_finalize_smm(void) +void intel_me8_finalize_smm(void) { struct me_hfs hfs; u32 reg32; |