diff options
| -rw-r--r-- | src/mainboard/google/cherry/Kconfig | 25 | ||||
| -rw-r--r-- | src/mainboard/google/cherry/Kconfig.name | 5 | ||||
| -rw-r--r-- | src/mainboard/google/cherry/Makefile.inc | 13 | ||||
| -rw-r--r-- | src/mainboard/google/cherry/board_info.txt | 6 | ||||
| -rw-r--r-- | src/mainboard/google/cherry/chromeos.c | 15 | ||||
| -rw-r--r-- | src/mainboard/google/cherry/chromeos.fmd | 45 | ||||
| -rw-r--r-- | src/mainboard/google/cherry/devicetree.cb | 7 | ||||
| -rw-r--r-- | src/mainboard/google/cherry/memlayout.ld | 3 | ||||
| -rw-r--r-- | src/mainboard/google/cherry/reset.c | 7 |
9 files changed, 126 insertions, 0 deletions
diff --git a/src/mainboard/google/cherry/Kconfig b/src/mainboard/google/cherry/Kconfig new file mode 100644 index 0000000000..8c7c093245 --- /dev/null +++ b/src/mainboard/google/cherry/Kconfig @@ -0,0 +1,25 @@ +## SPDX-License-Identifier: GPL-2.0-only + +# Umbrella option to be selected by variant boards. +config BOARD_GOOGLE_CHERRY_COMMON + def_bool n + +if BOARD_GOOGLE_CHERRY_COMMON + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_MEDIATEK_MT8195 + select BOARD_ROMSIZE_KB_8192 + select MAINBOARD_HAS_CHROMEOS + select COMMON_CBFS_SPI_WRAPPER + select SPI_FLASH + select SPI_FLASH_INCLUDE_ALL_DRIVERS + +config MAINBOARD_DIR + string + default "google/cherry" + +config MAINBOARD_PART_NUMBER + string + default "Cherry" if BOARD_GOOGLE_CHERRY +endif diff --git a/src/mainboard/google/cherry/Kconfig.name b/src/mainboard/google/cherry/Kconfig.name new file mode 100644 index 0000000000..8690b227f4 --- /dev/null +++ b/src/mainboard/google/cherry/Kconfig.name @@ -0,0 +1,5 @@ +comment "Cherry" + +config BOARD_GOOGLE_CHERRY + bool "-> Cherry" + select BOARD_GOOGLE_CHERRY_COMMON diff --git a/src/mainboard/google/cherry/Makefile.inc b/src/mainboard/google/cherry/Makefile.inc new file mode 100644 index 0000000000..ada29aa0d1 --- /dev/null +++ b/src/mainboard/google/cherry/Makefile.inc @@ -0,0 +1,13 @@ +bootblock-y += memlayout.ld +bootblock-y += chromeos.c + +verstage-y += memlayout.ld +verstage-y += chromeos.c +verstage-y += reset.c + +romstage-y += memlayout.ld +romstage-y += chromeos.c + +ramstage-y += memlayout.ld +ramstage-y += chromeos.c +ramstage-y += reset.c diff --git a/src/mainboard/google/cherry/board_info.txt b/src/mainboard/google/cherry/board_info.txt new file mode 100644 index 0000000000..72380c75ab --- /dev/null +++ b/src/mainboard/google/cherry/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Cherry MediaTek MT8195 reference board +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/cherry/chromeos.c b/src/mainboard/google/cherry/chromeos.c new file mode 100644 index 0000000000..3f0937f693 --- /dev/null +++ b/src/mainboard/google/cherry/chromeos.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <bootmode.h> +#include <boot/coreboot_tables.h> + +void fill_lb_gpios(struct lb_gpios *gpios) +{ + +} + +int get_recovery_mode_switch(void) +{ + /* TODO: use Chrome EC switches when EC support is added */ + return 0; +} diff --git a/src/mainboard/google/cherry/chromeos.fmd b/src/mainboard/google/cherry/chromeos.fmd new file mode 100644 index 0000000000..7194632e36 --- /dev/null +++ b/src/mainboard/google/cherry/chromeos.fmd @@ -0,0 +1,45 @@ +# Firmware Layout Description for Chrome OS. +# +# The size and address of every section must be aligned to at least 4K, except: +# RO_FRID, RW_FWID*, GBB, or any unused / padding / CBFS type sections. +# +# 'FMAP' may be found by binary search so its starting address should be better +# aligned to larger values. +# +# For sections to be preserved on update, add (PRESERVE) to individual sections +# instead of a group section; otherwise the preserved data may be wrong if you +# resize or reorder sections inside a group. + +FLASH@0x0 8M { + WP_RO@0x0 4M { + RO_SECTION { + BOOTBLOCK 128K + FMAP 4K + COREBOOT(CBFS) + GBB 0x2f00 + RO_FRID 0x100 + } + RO_VPD(PRESERVE) 32K # At least 16K. + } + RW_SECTION_A 1500K { + VBLOCK_A 8K + FW_MAIN_A(CBFS) + RW_FWID_A 0x100 + } + RW_MISC 36K { + RW_VPD(PRESERVE) 16K # At least 8K. + RW_NVRAM(PRESERVE) 8K + RW_MRC_CACHE(PRESERVE) 8K + RW_ELOG(PRESERVE) 4K # ELOG driver hard-coded size in 4K. + } + RW_SECTION_B 1500K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 0x100 + } + RW_SHARED 36K { # Will be force updated on recovery. + SHARED_DATA 4K # 4K or less for netboot params. + RW_UNUSED + } + RW_LEGACY(CBFS) 1M # Minimal 1M. +} diff --git a/src/mainboard/google/cherry/devicetree.cb b/src/mainboard/google/cherry/devicetree.cb new file mode 100644 index 0000000000..17fccc2d29 --- /dev/null +++ b/src/mainboard/google/cherry/devicetree.cb @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-only + +chip soc/mediatek/mt8195 + device cpu_cluster 0 on + device cpu 0 on end + end +end diff --git a/src/mainboard/google/cherry/memlayout.ld b/src/mainboard/google/cherry/memlayout.ld new file mode 100644 index 0000000000..0f1fcec9a0 --- /dev/null +++ b/src/mainboard/google/cherry/memlayout.ld @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <soc/memlayout.ld> diff --git a/src/mainboard/google/cherry/reset.c b/src/mainboard/google/cherry/reset.c new file mode 100644 index 0000000000..3a97ee5393 --- /dev/null +++ b/src/mainboard/google/cherry/reset.c @@ -0,0 +1,7 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <reset.h> + +void do_board_reset(void) +{ +} |