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-rw-r--r--src/cpu/samsung/exynos5250/chip.h2
-rw-r--r--src/cpu/samsung/exynos5420/chip.h2
-rw-r--r--src/drivers/intel/gma/i915.h3
-rw-r--r--src/drivers/intel/gma/intel_ddi.c4
-rw-r--r--src/drivers/intel/gma/intel_dp.c72
-rw-r--r--src/include/edid.h22
-rw-r--r--src/include/vbe.h2
-rw-r--r--src/lib/edid.c23
-rw-r--r--src/mainboard/google/link/i915.c2
-rw-r--r--src/mainboard/google/peppy/Kconfig3
-rw-r--r--src/mainboard/google/peppy/Makefile.inc1
-rw-r--r--src/mainboard/google/peppy/gma.c434
-rw-r--r--src/mainboard/google/peppy/i915io.c144
-rw-r--r--src/mainboard/google/peppy/mainboard.h25
-rw-r--r--src/mainboard/google/pit/devicetree.cb2
-rw-r--r--src/mainboard/google/pit/mainboard.c2
-rw-r--r--src/mainboard/google/slippy/gma.c6
-rw-r--r--src/mainboard/google/snow/devicetree.cb2
-rw-r--r--src/mainboard/google/snow/mainboard.c2
-rw-r--r--src/northbridge/intel/haswell/gma.c15
-rw-r--r--src/northbridge/intel/nehalem/gma.c2
21 files changed, 701 insertions, 69 deletions
diff --git a/src/cpu/samsung/exynos5250/chip.h b/src/cpu/samsung/exynos5250/chip.h
index f2443798d8..c2e7fb500d 100644
--- a/src/cpu/samsung/exynos5250/chip.h
+++ b/src/cpu/samsung/exynos5250/chip.h
@@ -34,7 +34,7 @@ struct cpu_samsung_exynos5250_config {
int xres;
int yres;
- int bpp;
+ int framebuffer_bits_per_pixel;
int usb_vbus_gpio;
int usb_hsic_gpio;
diff --git a/src/cpu/samsung/exynos5420/chip.h b/src/cpu/samsung/exynos5420/chip.h
index f2c710df50..220a315380 100644
--- a/src/cpu/samsung/exynos5420/chip.h
+++ b/src/cpu/samsung/exynos5420/chip.h
@@ -34,7 +34,7 @@ struct cpu_samsung_exynos5420_config {
int xres;
int yres;
- int bpp;
+ int framebuffer_bits_per_pixel;
int usb_vbus_gpio;
int usb_hsic_gpio;
diff --git a/src/drivers/intel/gma/i915.h b/src/drivers/intel/gma/i915.h
index 72301e1477..e8940a3b98 100644
--- a/src/drivers/intel/gma/i915.h
+++ b/src/drivers/intel/gma/i915.h
@@ -139,7 +139,7 @@ struct intel_dp {
int port;
int pipe;
int plane;
- int bpp;
+ int pipe_bits_per_pixel;
/* i2c on aux is ... interesting.
* Before you do an i2c cycle, you need to set the address.
* This requires we remember it from one moment to the next.
@@ -272,6 +272,7 @@ int intel_dp_get_lane_align_status(struct intel_dp *intel_dp,
void intel_prepare_ddi(void);
void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp);
+int gtt_poll(u32 reg, u32 mask, u32 value);
void gtt_write(u32 reg, u32 data);
u32 gtt_read(u32 reg);
diff --git a/src/drivers/intel/gma/intel_ddi.c b/src/drivers/intel/gma/intel_ddi.c
index 2b27f6eb65..e51fb9ce13 100644
--- a/src/drivers/intel/gma/intel_ddi.c
+++ b/src/drivers/intel/gma/intel_ddi.c
@@ -253,7 +253,7 @@ void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp)
{
u32 val = TRANS_MSA_SYNC_CLK;
- switch (intel_dp->bpp) {
+ switch (intel_dp->pipe_bits_per_pixel) {
case 18:
val |= TRANS_MSA_6_BPC;
break;
@@ -267,7 +267,7 @@ void intel_ddi_set_pipe_settings(struct intel_dp *intel_dp)
val |= TRANS_MSA_12_BPC;
break;
default:
- printk(BIOS_ERR, "Invalid bpp settings %d\n", intel_dp->bpp);
+ printk(BIOS_ERR, "Invalid bpp settings %d\n", intel_dp->pipe_bits_per_pixel);
}
gtt_write(TRANS_MSA_MISC(intel_dp->transcoder),val);
}
diff --git a/src/drivers/intel/gma/intel_dp.c b/src/drivers/intel/gma/intel_dp.c
index 833a4d6834..393692bd04 100644
--- a/src/drivers/intel/gma/intel_dp.c
+++ b/src/drivers/intel/gma/intel_dp.c
@@ -260,7 +260,7 @@ int intel_dp_set_bw(struct intel_dp *intel_dp)
int intel_dp_set_lane_count(struct intel_dp *intel_dp)
{
- printk(BIOS_SPEW, "DP_LANE_COUNT_SET");
+ printk(BIOS_SPEW, "DP_LANE_COUNT_SET %d ", intel_dp->lane_count);
return intel_dp_aux_native_write_1(intel_dp,
DP_LANE_COUNT_SET,
intel_dp->lane_count);
@@ -471,7 +471,24 @@ unsigned int roundup_power_of_two(unsigned int n)
static void compute_m_n(unsigned int m, unsigned int n,
unsigned int *ret_m, unsigned int *ret_n)
{
- *ret_n = MIN(roundup_power_of_two(n), DATA_LINK_N_MAX);
+ /* We noticed in the IO operations that
+ * the VBIOS was setting N to DATA_LINK_N_MAX.
+ * This makes sense, actually: the bigger N is, i.e.
+ * the bigger the denominator is, the bigger
+ * the numerator can be, and the more
+ * bits of numerator you get, the better the result.
+ * So, first pick the max of the two powers of two.
+ * And, in the (unlikely) event that you end up with
+ * something bigger than DATA_LINK_N_MAX, catch that
+ * case with a MIN. Note the second case is unlikely,
+ * but we are best off being careful.
+ */
+ /*
+ * This code is incorrect and will always set ret_n
+ * to DATA_LINK_N_MAX.
+ */
+ *ret_n = MAX(roundup_power_of_two(n), DATA_LINK_N_MAX);
+ *ret_n = MIN(*ret_n, DATA_LINK_N_MAX);
*ret_m = ( (unsigned long long)m * *ret_n) / n;
intel_reduce_m_n_ratio(ret_m, ret_n);
}
@@ -483,7 +500,6 @@ void intel_dp_compute_m_n(unsigned int bits_per_pixel,
struct intel_dp_m_n *m_n)
{
m_n->tu = 64;
-
compute_m_n(bits_per_pixel * pixel_clock,
link_clock * nlanes * 8,
&m_n->gmch_m, &m_n->gmch_n);
@@ -492,35 +508,6 @@ void intel_dp_compute_m_n(unsigned int bits_per_pixel,
&m_n->link_m, &m_n->link_n);
}
-/* not sure. */
-void intel_dp_set_m_n(struct intel_dp *intel_dp);
-
-void
-intel_dp_set_m_n(struct intel_dp *intel_dp)
-{
- int lane_count;
- struct intel_dp_m_n m_n;
- int pipe = intel_dp->pipe;
-
- lane_count = intel_dp->lane_count;
-
- /*
- * Compute the GMCH and Link ratios. The '3' here is
- * the number of bytes_per_pixel post-LUT, which we always
- * set up for 8-bits of R/G/B, or 3 bytes total.
- */
- intel_dp_compute_m_n(intel_dp->bpp, lane_count,
- intel_dp->clock, intel_dp->clock, &m_n);
-
- {
- gtt_write(TRANSDATA_M1(pipe),
- ((m_n.tu - 1) << PIPE_GMCH_DATA_M_TU_SIZE_SHIFT) |m_n.gmch_m);
- gtt_write(TRANSDATA_N1(pipe),m_n.gmch_n);
- gtt_write(TRANSDPLINK_M1(pipe),m_n.link_m);
- gtt_write(TRANSDPLINK_N1(pipe),m_n.link_n);
- }
-}
-
static void ironlake_edp_pll_off(void);
void
@@ -1791,17 +1778,13 @@ intel_dp_get_max_downspread(struct intel_dp *intel_dp, u8 *max_downspread)
return 1;
}
-void intel_dp_set_m_n_regs(struct intel_dp *intel_dp)
+void intel_dp_set_m_n_regs(struct intel_dp *dp)
{
- gtt_write(PIPE_DATA_M1(intel_dp->transcoder),0x7e4a0000);
- /* gtt_write(0x6f034,0x00800000); */
- /* Write to 0x6f030 has to be 0x7e4ayyyy -- First four hex digits are important.
- However, with our formula we always see values 0x7e43yyyy (1366 panel) and
- 0x7e42yyy (1280 panel) */
- /* gtt_write(PIPE_DATA_M1(intel_dp->transcoder),TU_SIZE(intel_dp->m_n.tu) | intel_dp->m_n.gmch_m); */
- gtt_write(PIPE_DATA_N1(intel_dp->transcoder),intel_dp->m_n.gmch_n);
- gtt_write(PIPE_LINK_M1(intel_dp->transcoder),intel_dp->m_n.link_m);
- gtt_write(PIPE_LINK_N1(intel_dp->transcoder),intel_dp->m_n.link_n);
+ gtt_write(PIPE_DATA_M1(dp->transcoder),
+ TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
+ gtt_write(PIPE_DATA_N1(dp->transcoder),dp->m_n.gmch_n);
+ gtt_write(PIPE_LINK_M1(dp->transcoder),dp->m_n.link_m);
+ gtt_write(PIPE_LINK_N1(dp->transcoder),dp->m_n.link_n);
}
void intel_dp_set_resolution(struct intel_dp *intel_dp)
@@ -1826,10 +1809,13 @@ int intel_dp_get_training_pattern(struct intel_dp *intel_dp,
int intel_dp_get_lane_count(struct intel_dp *intel_dp,
u8 *recv)
{
- return intel_dp_aux_native_read_retry(intel_dp,
+ int val = intel_dp_aux_native_read_retry(intel_dp,
DP_LANE_COUNT_SET,
recv,
0);
+ *recv &= DP_LANE_COUNT_MASK;
+ printk(BIOS_SPEW, "Lane count %s:%d\n", val < 0 ? "fail" : "ok", *recv);
+ return val;
}
int intel_dp_get_lane_align_status(struct intel_dp *intel_dp,
diff --git a/src/include/edid.h b/src/include/edid.h
index 4a2f13858b..867a82ff28 100644
--- a/src/include/edid.h
+++ b/src/include/edid.h
@@ -35,7 +35,27 @@ struct edid {
unsigned int version[2];
unsigned int nonconformant;
unsigned int type;
- unsigned int bpp;
+ /* These next three things used to all be called bpp.
+ * Merriment ensued. The identifier
+ * 'bpp' is herewith banished from our
+ * Kingdom.
+ */
+ /* How many bits in the framebuffer per pixel.
+ * Under all reasonable circumstances, it's 32.
+ */
+ unsigned int framebuffer_bits_per_pixel;
+ /* On the panel, how many bits per color?
+ * In almost all cases, it's 6 or 8.
+ * The standard allows for much more!
+ */
+ unsigned int panel_bits_per_color;
+ /* On the panel, how many bits per pixel.
+ * On Planet Earth, there are three colors
+ * per pixel, but this is convenient to have here
+ * instead of having 3*panel_bits_per_color
+ * all over the place.
+ */
+ unsigned int panel_bits_per_pixel;
unsigned int xres;
unsigned int yres;
unsigned int voltage;
diff --git a/src/include/vbe.h b/src/include/vbe.h
index 8ad9d2eb31..009dabd531 100644
--- a/src/include/vbe.h
+++ b/src/include/vbe.h
@@ -20,7 +20,7 @@ typedef struct {
u16 screen_width;
u16 screen_height;
u16 screen_linebytes; // bytes per line in framebuffer, may be more than screen_width
- u8 color_depth; // color depth in bpp
+ u8 color_depth; // color depth in bits per pixel
u32 framebuffer_address;
u8 edid_block_zero[128];
} __attribute__ ((__packed__)) screen_info_t;
diff --git a/src/lib/edid.c b/src/lib/edid.c
index 5c2d964efe..1ad9fea9cb 100644
--- a/src/lib/edid.c
+++ b/src/lib/edid.c
@@ -473,12 +473,18 @@ detailed_block(struct edid *out, unsigned char *x, int in_extension)
* rgb888 (i.e. no alpha, but pixels on 32-bit boundaries)
* The mainboard can modify these if needed, though
* we have yet to see a case where that will happen.
+ * The existing ARM mainboards don't even call this function
+ * so this will not affect them.
*/
- out->bpp = 32;
+ out->framebuffer_bits_per_pixel = 32;
- out->x_resolution = ALIGN(out->ha * ((out->bpp + 7) / 8),64) / (out->bpp/8);
+ out->x_resolution = ALIGN(out->ha *
+ ((out->framebuffer_bits_per_pixel + 7) / 8),
+ 64) / (out->framebuffer_bits_per_pixel/8);
out->y_resolution = out->va;
- out->bytes_per_line = ALIGN(out->ha * ((out->bpp + 7) / 8),64);
+ out->bytes_per_line = ALIGN(out->ha *
+ ((out->framebuffer_bits_per_pixel + 7)/8),
+ 64);
printk(BIOS_SPEW, "Did detailed timing\n");
}
did_detailed_timing = 1;
@@ -1064,7 +1070,8 @@ int decode_edid(unsigned char *edid, int size, struct edid *out)
else
printk(BIOS_SPEW, "%d bits per primary color channel\n",
((edid[0x14] & 0x70) >> 3) + 4);
- out->bpp = ((edid[0x14] & 0x70) >> 3) + 4;
+ out->panel_bits_per_color = ((edid[0x14] & 0x70) >> 3) + 4;
+ out->panel_bits_per_pixel = 3*out->panel_bits_per_color;
switch (edid[0x14] & 0x0f) {
case 0x00: printk(BIOS_SPEW, "Digital interface is not defined\n"); break;
@@ -1423,7 +1430,7 @@ void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr)
edid_fb.x_resolution = edid->x_resolution;
edid_fb.y_resolution = edid->y_resolution;
edid_fb.bytes_per_line = edid->bytes_per_line;
- /* In the case of (e.g.) 24bpp, the convention nowadays
+ /* In the case of (e.g.) 24 framebuffer bits per pixel, the convention nowadays
* seems to be to round it up to the nearest reasonable
* boundary, because otherwise the byte-packing is hideous.
* So, for example, in RGB with no alpha, the bytes are still
@@ -1434,8 +1441,8 @@ void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr)
* It's not clear we're covering all cases here, but
* I'm not sure with grahpics you ever can.
*/
- edid_fb.bits_per_pixel = edid->bpp;
- switch(edid->bpp){
+ edid_fb.bits_per_pixel = edid->framebuffer_bits_per_pixel;
+ switch(edid->framebuffer_bits_per_pixel){
case 32:
case 24:
/* packed into 4-byte words */
@@ -1457,7 +1464,7 @@ void set_vbe_mode_info_valid(struct edid *edid, uintptr_t fb_addr)
break;
default:
printk(BIOS_SPEW, "%s: unsupported BPP %d\n", __func__,
- edid->bpp);
+ edid->framebuffer_bits_per_pixel);
return;
}
diff --git a/src/mainboard/google/link/i915.c b/src/mainboard/google/link/i915.c
index 233148c698..8d94d36b7a 100644
--- a/src/mainboard/google/link/i915.c
+++ b/src/mainboard/google/link/i915.c
@@ -258,7 +258,7 @@ int i915lightup(const struct northbridge_intel_sandybridge_config *info,
edid_ok = decode_edid((unsigned char *)&link_edid_data,
sizeof(link_edid_data), &edid);
printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
- edid.bpp = 32;
+ edid.framebuffer_bits_per_pixel = 32;
htotal = (edid.ha - 1) | ((edid.ha + edid.hbl- 1) << 16);
printk(BIOS_SPEW, "I915_WRITE(HTOTAL(pipe), %08x)\n", htotal);
diff --git a/src/mainboard/google/peppy/Kconfig b/src/mainboard/google/peppy/Kconfig
index cae34ff106..548cd17cd7 100644
--- a/src/mainboard/google/peppy/Kconfig
+++ b/src/mainboard/google/peppy/Kconfig
@@ -18,6 +18,9 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select MAINBOARD_HAS_CHROMEOS
select EXTERNAL_MRC_BLOB
select MONOTONIC_TIMER_MSR
+ select MAINBOARD_HAS_NATIVE_VGA_INIT
+ select INTEL_DP
+ select INTEL_DDI
config VBOOT_RAMSTAGE_INDEX
hex
diff --git a/src/mainboard/google/peppy/Makefile.inc b/src/mainboard/google/peppy/Makefile.inc
index 21c4c967e9..86b908289f 100644
--- a/src/mainboard/google/peppy/Makefile.inc
+++ b/src/mainboard/google/peppy/Makefile.inc
@@ -21,6 +21,7 @@ ramstage-$(CONFIG_EC_GOOGLE_CHROMEEC) += ec.c
romstage-y += chromeos.c
ramstage-y += chromeos.c
+ramstage-$(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) += gma.c i915io.c
smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c
diff --git a/src/mainboard/google/peppy/gma.c b/src/mainboard/google/peppy/gma.c
new file mode 100644
index 0000000000..c03805ef1a
--- /dev/null
+++ b/src/mainboard/google/peppy/gma.c
@@ -0,0 +1,434 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2013 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <stdlib.h>
+#include <device/device.h>
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+#include <delay.h>
+#include <pc80/mc146818rtc.h>
+#include <arch/acpi.h>
+#include <arch/io.h>
+#include <arch/interrupt.h>
+#include <boot/coreboot_tables.h>
+#include "hda_verb.h"
+#include <smbios.h>
+#include <device/pci.h>
+#include <ec/google/chromeec/ec.h>
+#include <cbfs_core.h>
+
+#include <cpu/x86/tsc.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <edid.h>
+#include <drivers/intel/gma/i915.h>
+#include "mainboard.h"
+
+/*
+ * Here is the rough outline of how we bring up the display:
+ * 1. Upon power-on Sink generates a hot plug detection pulse thru HPD
+ * 2. Source determines video mode by reading DPCD receiver capability field
+ * (DPCD 00000h to 0000Dh) including eDP CP capability register (DPCD
+ * 0000Dh).
+ * 3. Sink replies DPCD receiver capability field.
+ * 4. Source starts EDID read thru I2C-over-AUX.
+ * 5. Sink replies EDID thru I2C-over-AUX.
+ * 6. Source determines link configuration, such as MAX_LINK_RATE and
+ * MAX_LANE_COUNT. Source also determines which type of eDP Authentication
+ * method to use and writes DPCD link configuration field (DPCD 00100h to
+ * 0010Ah) including eDP configuration set (DPCD 0010Ah).
+ * 7. Source starts link training. Sink does clock recovery and equalization.
+ * 8. Source reads DPCD link status field (DPCD 00200h to 0020Bh).
+ * 9. Sink replies DPCD link status field. If main link is not stable, Source
+ * repeats Step 7.
+ * 10. Source sends MSA (Main Stream Attribute) data. Sink extracts video
+ * parameters and recovers stream clock.
+ * 11. Source sends video data.
+ */
+
+/* how many bytes do we need for the framebuffer?
+ * Well, this gets messy. To get an exact answer, we have
+ * to ask the panel, but we'd rather zero the memory
+ * and set up the gtt while the panel powers up. So,
+ * we take a reasonable guess, secure in the knowledge that the
+ * MRC has to overestimate the number of bytes used.
+ * 8 MiB is a very safe guess. There may be a better way later, but
+ * fact is, the initial framebuffer is only very temporary. And taking
+ * a little long is ok; this is done much faster than the AUX
+ * channel is ready for IO.
+ */
+#define FRAME_BUFFER_BYTES (8*MiB)
+/* how many 4096-byte pages do we need for the framebuffer?
+ * There are hard ways to get this, and easy ways:
+ * there are FRAME_BUFFER_BYTES/4096 pages, since pages are 4096
+ * on this chip (and in fact every Intel graphics chip we've seen).
+ */
+#define FRAME_BUFFER_PAGES (FRAME_BUFFER_BYTES/(4096))
+
+static unsigned int *mmio;
+static unsigned int graphics;
+static unsigned int physbase;
+
+/* GTT is the Global Translation Table for the graphics pipeline.
+ * It is used to translate graphics addresses to physical
+ * memory addresses. As in the CPU, GTTs map 4K pages.
+ * The setgtt function adds a further bit of flexibility:
+ * it allows you to set a range (the first two parameters) to point
+ * to a physical address (third parameter);the physical address is
+ * incremented by a count (fourth parameter) for each GTT in the
+ * range.
+ * Why do it this way? For ultrafast startup,
+ * we can point all the GTT entries to point to one page,
+ * and set that page to 0s:
+ * memset(physbase, 0, 4096);
+ * setgtt(0, 4250, physbase, 0);
+ * this takes about 2 ms, and is a win because zeroing
+ * the page takes a up to 200 ms.
+ * This call sets the GTT to point to a linear range of pages
+ * starting at physbase.
+ */
+
+#define GTT_PTE_BASE (2 << 20)
+
+int intel_dp_bw_code_to_link_rate(u8 link_bw);
+
+static void
+setgtt(int start, int end, unsigned long base, int inc)
+{
+ int i;
+
+ for(i = start; i < end; i++){
+ u32 word = base + i*inc;
+ /* note: we've confirmed by checking
+ * the values that mrc does no
+ * useful setup before we run this.
+ */
+ gtt_write(GTT_PTE_BASE + i * 4, word|1);
+ gtt_read(GTT_PTE_BASE + i * 4);
+ }
+}
+
+static int i915_init_done = 0;
+
+/* fill the palette. */
+static void palette(void)
+{
+ int i;
+ unsigned long color = 0;
+
+ for(i = 0; i < 256; i++, color += 0x010101){
+ gtt_write(_LGC_PALETTE_A + (i<<2),color);
+ }
+}
+
+/* assumption: the dpcd in the dp is valid. The raw edid has been read
+ * and the translation has been done.
+ */
+void dp_init_dim_regs(struct intel_dp *dp);
+void dp_init_dim_regs(struct intel_dp *dp)
+{
+ struct edid *edid = &(dp->edid);
+
+ /* step 1: get the constants in the dp struct set up. */
+ dp->lane_count = dp->dpcd[DP_MAX_LANE_COUNT]&DP_LANE_COUNT_MASK;
+
+ dp->link_bw = dp->dpcd[DP_MAX_LINK_RATE];
+ dp->clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
+ dp->edid.link_clock = intel_dp_bw_code_to_link_rate(dp->link_bw);
+
+ /* step 2. Do some computation of other stuff. */
+ dp->bytes_per_pixel = dp->pipe_bits_per_pixel/8;
+
+ dp->stride = edid->bytes_per_line;
+
+ dp->htotal = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
+
+ dp->hblank = (edid->ha - 1) | ((edid->ha + edid->hbl - 1) << 16);
+
+ dp->hsync = (edid->ha + edid->hso - 1) |
+ ((edid->ha + edid->hso + edid->hspw - 1) << 16);
+
+ dp->vtotal = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
+
+ dp->vblank = (edid->va - 1) | ((edid->va + edid->vbl - 1) << 16);
+
+ dp->vsync = (edid->va + edid->vso - 1) |
+ ((edid->va + edid->vso + edid->vspw - 1) << 16);
+
+ /* PIPEASRC is wid-1 x ht-1 */
+ dp->pipesrc = (edid->ha-1)<<16 | (edid->va-1);
+
+ dp->pfa_pos = 0;
+
+ /* XXXXXXXXXXXXXX hard code */
+ dp->pfa_ctl = 0x80800000;
+
+ dp->pfa_sz = (edid->ha << 16) | (edid->va);
+
+ /* step 3. Call the linux code we pulled in. */
+ dp->flags = intel_ddi_calc_transcoder_flags(edid->panel_bits_per_pixel,
+ dp->port,
+ dp->pipe,
+ dp->type,
+ dp->lane_count,
+ dp->pfa_sz,
+ dp->edid.phsync == '+'?1:0,
+ dp->edid.pvsync == '+'?1:0);
+
+ dp->transcoder = intel_ddi_get_transcoder(dp->port,
+ dp->pipe);
+
+ intel_dp_compute_m_n(edid->panel_bits_per_pixel,
+ dp->lane_count,
+ dp->edid.pixel_clock,
+ dp->edid.link_clock,
+ &dp->m_n);
+
+ printk(BIOS_SPEW, "dp->lane_count = 0x%08x\n",dp->lane_count);
+ printk(BIOS_SPEW, "dp->stride = 0x%08x\n",dp->stride);
+ printk(BIOS_SPEW, "dp->htotal = 0x%08x\n", dp->htotal);
+ printk(BIOS_SPEW, "dp->hblank = 0x%08x\n", dp->hblank);
+ printk(BIOS_SPEW, "dp->hsync = 0x%08x\n", dp->hsync);
+ printk(BIOS_SPEW, "dp->vtotal = 0x%08x\n", dp->vtotal);
+ printk(BIOS_SPEW, "dp->vblank = 0x%08x\n", dp->vblank);
+ printk(BIOS_SPEW, "dp->vsync = 0x%08x\n", dp->vsync);
+ printk(BIOS_SPEW, "dp->pipesrc = 0x%08x\n", dp->pipesrc);
+ printk(BIOS_SPEW, "dp->pfa_pos = 0x%08x\n", dp->pfa_pos);
+ printk(BIOS_SPEW, "dp->pfa_ctl = 0x%08x\n", dp->pfa_ctl);
+ printk(BIOS_SPEW, "dp->pfa_sz = 0x%08x\n", dp->pfa_sz);
+ printk(BIOS_SPEW, "dp->link_m = 0x%08x\n", dp->m_n.link_m);
+ printk(BIOS_SPEW, "dp->link_n = 0x%08x\n", dp->m_n.link_n);
+ printk(BIOS_SPEW, "0x6f030 = 0x%08x\n",
+ TU_SIZE(dp->m_n.tu) | dp->m_n.gmch_m);
+ printk(BIOS_SPEW, "0x6f030 = 0x%08x\n", dp->m_n.gmch_m);
+ printk(BIOS_SPEW, "0x6f034 = 0x%08x\n", dp->m_n.gmch_n);
+ printk(BIOS_SPEW, "dp->flags = 0x%08x\n", dp->flags);
+}
+
+int intel_dp_bw_code_to_link_rate(u8 link_bw)
+{
+ switch (link_bw) {
+ default:
+ printk(BIOS_ERR,
+ "ERROR: link_bw(%d) is bogus; must be one of 6, 0xa, or 0x14\n",
+ link_bw);
+ case DP_LINK_BW_1_62:
+ return 162000;
+ case DP_LINK_BW_2_7:
+ return 270000;
+ case DP_LINK_BW_5_4:
+ return 540000;
+ }
+}
+
+void mainboard_train_link(struct intel_dp *intel_dp)
+{
+ u8 read_val;
+ u8 link_status[DP_LINK_STATUS_SIZE];
+
+ gtt_write(DP_TP_CTL(intel_dp->port),
+ DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE);
+ gtt_write(DDI_BUF_CTL_A,
+ DDI_BUF_CTL_ENABLE|
+ DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|0x80000011);
+
+ intel_dp_get_training_pattern(intel_dp, &read_val);
+ intel_dp_set_training_pattern(intel_dp,
+ DP_TRAINING_PATTERN_1 | DP_LINK_QUAL_PATTERN_DISABLE |
+ DP_SYMBOL_ERROR_COUNT_BOTH);
+
+ intel_dp_set_training_lane0(intel_dp,
+ DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0);
+ intel_dp_get_link_status(intel_dp, link_status);
+
+ gtt_write(DP_TP_CTL(intel_dp->port),
+ DP_TP_CTL_ENABLE |
+ DP_TP_CTL_ENHANCED_FRAME_ENABLE | DP_TP_CTL_LINK_TRAIN_PAT2);
+
+ intel_dp_get_training_pattern(intel_dp, &read_val);
+ intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_2 |
+ DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
+ intel_dp_get_link_status(intel_dp, link_status);
+ intel_dp_get_lane_align_status(intel_dp, &read_val);
+ intel_dp_get_training_pattern(intel_dp, &read_val);
+ intel_dp_set_training_pattern(intel_dp, DP_TRAINING_PATTERN_DISABLE |
+ DP_LINK_QUAL_PATTERN_DISABLE | DP_SYMBOL_ERROR_COUNT_BOTH);
+}
+
+/* This variable controls whether the test_gfx function below puts up
+ * color bars or not. In previous revs we ifdef'd the test_gfx function out
+ * but it's handy, especially when using a JTAG debugger
+ * to be able to enable and disable a test graphics.
+ */
+int show_test = 0;
+
+static void test_gfx(struct intel_dp *dp)
+{
+ int i;
+
+ if (!show_test)
+ return;
+ /* This is a sanity test code which fills the screen with two bands --
+ green and blue. It is very useful to ensure all the initializations
+ are made right. Thus, to be used only for testing, not otherwise
+ */
+ printk(BIOS_SPEW, "TEST: graphics %p, va %d, ha %d, stride %d\n",
+ (u32 *)graphics, dp->edid.va, dp->edid.ha, dp->stride);
+
+ for (i = 0; i < (dp->edid.va - 4); i++) {
+ u32 *l;
+ int j;
+ u32 tcolor = 0x0ff;
+ for (j = 0; j < (dp->edid.ha-4); j++) {
+ if (j == (dp->edid.ha/2)) {
+ tcolor = 0xff00;
+ }
+ l = (u32*)(graphics + i * dp->stride + j * sizeof(tcolor));
+ memcpy(l,&tcolor,sizeof(tcolor));
+ }
+ }
+ printk(BIOS_SPEW, "sleep 10\n");
+ delay(10);
+}
+
+void mainboard_set_port_clk_dp(struct intel_dp *intel_dp)
+{
+ u32 ddi_pll_sel = 0;
+
+ switch (intel_dp->link_bw) {
+ case DP_LINK_BW_1_62:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_810;
+ break;
+ case DP_LINK_BW_2_7:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_1350;
+ break;
+ case DP_LINK_BW_5_4:
+ ddi_pll_sel = PORT_CLK_SEL_LCPLL_2700;
+ break;
+ default:
+ printk(BIOS_ERR, "invalid link bw %d\n", intel_dp->link_bw);
+ return;
+ }
+
+ gtt_write(PORT_CLK_SEL(intel_dp->port), ddi_pll_sel);
+}
+
+int i915lightup(unsigned int pphysbase, unsigned int pmmio,
+ unsigned int pgfx, unsigned int init_fb)
+{
+ int must_cycle_power = 0;
+ struct intel_dp adp, *dp = &adp;
+ int i;
+ int edid_ok;
+ int pixels = FRAME_BUFFER_BYTES/64;
+
+ gtt_write(PCH_PP_CONTROL,0xabcd000f);
+ delay(1);
+ mmio = (void *)pmmio;
+ physbase = pphysbase;
+ graphics = pgfx;
+ printk(BIOS_SPEW,
+ "i915lightup: graphics %p mmio %p"
+ "physbase %08x\n",
+ (void *)graphics, mmio, physbase);
+
+ void runio(struct intel_dp *dp);
+ /* hard codes -- stuff you can only know from the mainboard */
+ dp->gen = 8; // This is gen 8 which we believe is Haswell
+ dp->is_haswell = 1;
+ dp->DP = 0x2;
+ dp->pipe = PIPE_A;
+ dp->port = PORT_A;
+ dp->plane = PLANE_A;
+ dp->pipe_bits_per_pixel = 24;
+ dp->type = INTEL_OUTPUT_EDP;
+ dp->output_reg = DP_A;
+ /* observed from YABEL. */
+ dp->aux_clock_divider = 0xe1;
+ dp->precharge = 3;
+
+ /* CRAP -- needs to be done elsewhere from the device tree. */
+ dp->panel_power_down_delay = 600;
+ dp->panel_power_up_delay = 200;
+ dp->panel_power_cycle_delay = 600;
+
+ /* 1. Normal mode: Set the first page to zero and make
+ all GTT entries point to the same page
+ 2. Developer/Recovery mode: Set up a tasteful color
+ so people know we are alive. */
+ if (init_fb || show_test) {
+ setgtt(0, FRAME_BUFFER_PAGES, physbase, 4096);
+ memset((void *)graphics, 0x55, FRAME_BUFFER_PAGES*4096);
+ } else {
+ setgtt(0, FRAME_BUFFER_PAGES, physbase, 0);
+ memset((void*)graphics, 0, 4096);
+ }
+
+ dp->address = 0x50;
+
+ if ( !intel_dp_get_dpcd(dp) )
+ goto fail;
+
+ intel_dp_i2c_aux_ch(dp, MODE_I2C_WRITE, 0, NULL);
+ for(dp->edidlen = i = 0; i < sizeof(dp->rawedid); i++){
+ if (intel_dp_i2c_aux_ch(dp, MODE_I2C_READ,
+ 0x50, &dp->rawedid[i]) < 0)
+ break;
+ dp->edidlen++;
+ }
+
+ edid_ok = decode_edid(dp->rawedid, dp->edidlen, &dp->edid);
+
+ printk(BIOS_SPEW, "decode edid returns %d\n", edid_ok);
+
+ dp_init_dim_regs(dp);
+
+ printk(BIOS_SPEW, "pixel_clock is %i, link_clock is %i\n",
+ dp->edid.pixel_clock, dp->edid.link_clock);
+
+ intel_ddi_set_pipe_settings(dp);
+
+ runio(dp);
+
+ palette();
+
+ pixels = dp->edid.ha * (dp->edid.va-4) * 4;
+ printk(BIOS_SPEW, "ha=%d, va=%d\n",dp->edid.ha, dp->edid.va);
+ test_gfx(dp);
+
+ set_vbe_mode_info_valid(&dp->edid, graphics);
+ i915_init_done = 1;
+ return 1;
+
+fail:
+ printk(BIOS_SPEW, "Graphics could not be started;");
+ if (0 && must_cycle_power){
+ printk(BIOS_SPEW, "Turn off power and wait ...");
+ gtt_write(PCH_PP_CONTROL,0xabcd0000);
+ udelay(600000);
+ gtt_write(PCH_PP_CONTROL,0xabcd000f);
+ }
+ printk(BIOS_SPEW, "Returning.\n");
+ return 0;
+}
diff --git a/src/mainboard/google/peppy/i915io.c b/src/mainboard/google/peppy/i915io.c
new file mode 100644
index 0000000000..693aed5185
--- /dev/null
+++ b/src/mainboard/google/peppy/i915io.c
@@ -0,0 +1,144 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright 2013 Google Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; version 2 of the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#include <stdint.h>
+#include <console/console.h>
+#include <delay.h>
+#include <drivers/intel/gma/i915.h>
+#include <arch/io.h>
+#include "mainboard.h"
+
+void runio(struct intel_dp *dp, int verbose);
+void runio(struct intel_dp *dp, int verbose)
+{
+ u8 read_val;
+ gtt_write(DDI_BUF_CTL_A,
+ DDI_BUF_IS_IDLE|DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED
+ |0x00000091);
+
+ intel_prepare_ddi();
+
+ gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
+
+ gtt_write(DEIIR,0x00008000);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+ gtt_write(DSPSTRIDE(dp->plane), dp->stride);
+ gtt_write(DSPADDR(dp->plane), 0x00000000);
+
+ printk(BIOS_SPEW, "DP_SET_POWER");
+
+ intel_dp_sink_dpms(dp, 0);
+
+ intel_dp_set_m_n_regs(dp);
+
+ intel_dp_get_max_downspread(dp, &read_val);
+
+ intel_dp_set_resolution(dp);
+
+ gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
+ gtt_write(PIPECONF(dp->transcoder),0x00000000);
+ gtt_write(PCH_TRANSCONF(dp->pipe),0x00000000);
+
+ mainboard_set_port_clk_dp(dp);
+
+ gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+ gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE|DISPPLANE_RGBX888);
+
+ gtt_write(DEIIR,0x00000080);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+
+ /* There is some reason we removed these three calls from
+ * slippy/gma.c -- I dont remember why!! */
+ gtt_write(PF_WIN_POS(dp->pipe),dp->pfa_pos);
+ gtt_write(PF_CTL(dp->pipe),dp->pfa_ctl);
+ gtt_write(PF_WIN_SZ(dp->pipe),dp->pfa_sz);
+
+ gtt_write(TRANS_DDI_FUNC_CTL_EDP,dp->flags);
+ gtt_write(PIPECONF(dp->transcoder),PIPECONF_ENABLE|PIPECONF_DITHER_EN);
+
+ /* what is this doing? Not sure yet. But we don't seem to be
+ * able to live without it.*/
+ intel_dp_i2c_write(dp, 0x0);
+ intel_dp_i2c_read(dp, &read_val);
+ intel_dp_i2c_write(dp, 0x04);
+ intel_dp_i2c_read(dp, &read_val);
+ intel_dp_i2c_write(dp, 0x7e);
+ intel_dp_i2c_read(dp, &read_val);
+
+ gtt_write(DDI_BUF_CTL_A,
+ DDI_BUF_IS_IDLE|
+ DDI_A_4_LANES|DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED
+ |0x00000091);
+
+ gtt_write(TRANS_DDI_FUNC_CTL_EDP+0x10,0x00000001);
+ gtt_write(DP_TP_CTL(dp->port),DP_TP_CTL_ENABLE |
+ DP_TP_CTL_ENHANCED_FRAME_ENABLE);
+
+ gtt_write(DDI_BUF_CTL_A,
+ DDI_BUF_CTL_ENABLE|
+ /* another undocumented setting. Surprised? */ 0x40000 |
+ DDI_BUF_IS_IDLE|DDI_A_4_LANES|
+ DDI_PORT_WIDTH_X1|DDI_INIT_DISPLAY_DETECTED|
+ 0x80040091);
+
+ intel_dp_set_bw(dp);
+
+ intel_dp_set_lane_count(dp);
+
+ mainboard_train_link(dp);
+
+ gtt_write(DP_TP_CTL(dp->port),
+ DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE |
+ DP_TP_CTL_LINK_TRAIN_IDLE);
+
+ gtt_write(DP_TP_CTL(dp->port),
+ DP_TP_CTL_ENABLE | DP_TP_CTL_ENHANCED_FRAME_ENABLE |
+ DP_TP_CTL_LINK_TRAIN_NORMAL);
+
+ gtt_write(BLC_PWM_CPU_CTL,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL2,0x03a903a9);
+ gtt_write(BLC_PWM_PCH_CTL1,0x80000000);
+
+ /* some of this is not needed. But with a total lack of docs, well ...*/
+ gtt_write(DIGITAL_PORT_HOTPLUG_CNTRL, DIGITAL_PORTA_HOTPLUG_ENABLE );
+
+ gtt_write(SDEIIR,0x00000000);
+ gtt_write(DEIIR,0x00000000);
+ gtt_write(DEIIR,0x00008000);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+
+ gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+ gtt_write(PIPESRC(dp->pipe),dp->pipesrc);
+
+ gtt_write(DEIIR,0x00000080);
+ intel_dp_wait_reg(DEIIR, 0x00000000);
+
+ gtt_write(DSPSTRIDE(dp->plane),dp->stride);
+ gtt_write(DSPCNTR(dp->plane),DISPLAY_PLANE_ENABLE | DISPPLANE_RGBX888);
+
+ gtt_write(PCH_PP_CONTROL,EDP_BLC_ENABLE | EDP_BLC_ENABLE | PANEL_POWER_ON);
+
+ gtt_write(SDEIIR,0x00000000);
+ gtt_write(SDEIIR,0x00000000);
+ gtt_write(DEIIR,0x00000000);
+
+}
+
diff --git a/src/mainboard/google/peppy/mainboard.h b/src/mainboard/google/peppy/mainboard.h
new file mode 100644
index 0000000000..f47fffda2a
--- /dev/null
+++ b/src/mainboard/google/peppy/mainboard.h
@@ -0,0 +1,25 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright 2013 Google Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; version 2 of the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+
+#ifndef __MAINBOARD_H_
+#define __MAINBOARD_H_
+void mainboard_train_link(struct intel_dp *intel_dp);
+void mainboard_set_port_clk_dp(struct intel_dp *intel_dp);
+
+#endif
diff --git a/src/mainboard/google/pit/devicetree.cb b/src/mainboard/google/pit/devicetree.cb
index 3b6cdb9014..687b75076f 100644
--- a/src/mainboard/google/pit/devicetree.cb
+++ b/src/mainboard/google/pit/devicetree.cb
@@ -21,7 +21,7 @@ chip cpu/samsung/exynos5420
device cpu_cluster 0 on end
register "xres" = "1366"
register "yres" = "768"
- register "bpp" = "16"
+ register "framebuffer_bits_per_pixel" = "16"
# complex magic timing!
register "clkval_f" = "2"
register "upper_margin" = "14"
diff --git a/src/mainboard/google/pit/mainboard.c b/src/mainboard/google/pit/mainboard.c
index 211160d754..5812a8445b 100644
--- a/src/mainboard/google/pit/mainboard.c
+++ b/src/mainboard/google/pit/mainboard.c
@@ -52,7 +52,7 @@
static struct edid edid = {
.ha = 1366,
.va = 768,
- .bpp = 16,
+ .framebuffer_bits_per_pixel = 16,
.x_resolution = 1366,
.y_resolution = 768,
.bytes_per_line = 2 * 1366
diff --git a/src/mainboard/google/slippy/gma.c b/src/mainboard/google/slippy/gma.c
index 839fa4dc2a..1e199128b9 100644
--- a/src/mainboard/google/slippy/gma.c
+++ b/src/mainboard/google/slippy/gma.c
@@ -150,7 +150,7 @@ void dp_init_dim_regs(struct intel_dp *dp)
{
struct edid *edid = &(dp->edid);
- dp->bytes_per_pixel = edid->bpp / 8;
+ dp->bytes_per_pixel = edid->framebuffer_bits_per_pixel / 8;
dp->stride = edid->bytes_per_line;
@@ -189,7 +189,7 @@ void dp_init_dim_regs(struct intel_dp *dp)
dp->transcoder = intel_ddi_get_transcoder(dp->port,
dp->pipe);
- intel_dp_compute_m_n(dp->bpp,
+ intel_dp_compute_m_n(dp->pipe_bits_per_pixel,
dp->lane_count,
dp->edid.pixel_clock,
dp->edid.link_clock,
@@ -336,7 +336,7 @@ int i915lightup(unsigned int pphysbase, unsigned int pmmio,
dp->port = PORT_A;
dp->plane = PLANE_A;
dp->clock = 160000;
- dp->bpp = 32;
+ dp->pipe_bits_per_pixel = 32;
dp->type = INTEL_OUTPUT_EDP;
dp->output_reg = DP_A;
/* observed from YABEL. */
diff --git a/src/mainboard/google/snow/devicetree.cb b/src/mainboard/google/snow/devicetree.cb
index c14f374d6d..e6ce49dcca 100644
--- a/src/mainboard/google/snow/devicetree.cb
+++ b/src/mainboard/google/snow/devicetree.cb
@@ -21,7 +21,7 @@ chip cpu/samsung/exynos5250
device cpu_cluster 0 on end
register "xres" = "1366"
register "yres" = "768"
- register "bpp" = "16"
+ register "framebuffer_bits_per_pixel" = "16"
# complex magic timing!
register "clkval_f" = "2"
register "upper_margin" = "14"
diff --git a/src/mainboard/google/snow/mainboard.c b/src/mainboard/google/snow/mainboard.c
index f906e534a3..5137d10c66 100644
--- a/src/mainboard/google/snow/mainboard.c
+++ b/src/mainboard/google/snow/mainboard.c
@@ -53,7 +53,7 @@
static struct edid edid = {
.ha = 1366,
.va = 768,
- .bpp = 16,
+ .framebuffer_bits_per_pixel = 16,
.x_resolution = 1366,
.y_resolution = 768,
.bytes_per_line = 2 * 1366
diff --git a/src/northbridge/intel/haswell/gma.c b/src/northbridge/intel/haswell/gma.c
index 9dfba9a316..057d65ad55 100644
--- a/src/northbridge/intel/haswell/gma.c
+++ b/src/northbridge/intel/haswell/gma.c
@@ -28,6 +28,7 @@
#include <drivers/intel/gma/i915.h>
#include <cpu/intel/haswell/haswell.h>
#include <stdlib.h>
+#include <string.h>
#include "chip.h"
#include "haswell.h"
@@ -130,7 +131,10 @@ static struct resource *gtt_res = NULL;
u32 gtt_read(u32 reg)
{
- return read32(gtt_res->base + reg);
+ u32 val;
+ val = read32(gtt_res->base + reg);
+ return val;
+
}
void gtt_write(u32 reg, u32 data)
@@ -157,7 +161,7 @@ static inline void gtt_write_regs(const struct gt_reg *gt)
}
#define GTT_RETRY 1000
-static int gtt_poll(u32 reg, u32 mask, u32 value)
+int gtt_poll(u32 reg, u32 mask, u32 value)
{
unsigned try = GTT_RETRY;
u32 data;
@@ -177,6 +181,13 @@ static void power_well_enable(void)
{
gtt_write(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_ENABLE);
gtt_poll(HSW_PWR_WELL_CTL1, HSW_PWR_WELL_STATE, HSW_PWR_WELL_STATE);
+#if CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT
+ /* In the native graphics case, we've got about 20 ms.
+ * after we power up the the AUX channel until we can talk to it.
+ * So get that going right now. We can't turn on the panel, yet, just VDD.
+ */
+ gtt_write(PCH_PP_CONTROL, PCH_PP_UNLOCK| EDP_FORCE_VDD | PANEL_POWER_RESET);
+#endif
}
static void gma_pm_init_pre_vbios(struct device *dev)
diff --git a/src/northbridge/intel/nehalem/gma.c b/src/northbridge/intel/nehalem/gma.c
index f76fbc4e15..a57bf6bd88 100644
--- a/src/northbridge/intel/nehalem/gma.c
+++ b/src/northbridge/intel/nehalem/gma.c
@@ -289,7 +289,7 @@ static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
}
#define GTT_RETRY 1000
-static int gtt_poll(u32 reg, u32 mask, u32 value)
+int gtt_poll(u32 reg, u32 mask, u32 value)
{
unsigned try = GTT_RETRY;
u32 data;
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-13 00:46:51 +0000