17 files changed, 567 insertions, 0 deletions

diff --git a/src/mainboard/asrock/b75m-itx/Kconfig b/src/mainboard/asrock/b75m-itx/Kconfig
new file mode 100644
index 0000000000..51d86f71db
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/Kconfig
@@ -0,0 +1,28 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+if BOARD_ASROCK_B75M_ITX
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_8192
+	select SUPERIO_NUVOTON_NCT6776
+	select NO_UART_ON_SUPERIO
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select HAVE_CMOS_DEFAULT
+	select HAVE_OPTION_TABLE
+	select INTEL_GMA_HAVE_VBT
+	select INTEL_INT15
+	select MAINBOARD_HAS_LIBGFXINIT
+	select NORTHBRIDGE_INTEL_SANDYBRIDGE
+	select SERIRQ_CONTINUOUS_MODE
+	select SOUTHBRIDGE_INTEL_C216
+	select USE_NATIVE_RAMINIT
+
+config MAINBOARD_DIR
+	default "asrock/b75m-itx"
+
+config MAINBOARD_PART_NUMBER
+	default "B75M-ITX"
+
+endif
diff --git a/src/mainboard/asrock/b75m-itx/Kconfig.name b/src/mainboard/asrock/b75m-itx/Kconfig.name
new file mode 100644
index 0000000000..40cab89515
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_ASROCK_B75M_ITX
+	bool "B75M-ITX"
diff --git a/src/mainboard/asrock/b75m-itx/Makefile.inc b/src/mainboard/asrock/b75m-itx/Makefile.inc
new file mode 100644
index 0000000000..d1b484d217
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/Makefile.inc
@@ -0,0 +1,8 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+bootblock-y += gpio.c
+romstage-y += gpio.c
+
+bootblock-y += early_init.c
+romstage-y += early_init.c
+ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads
diff --git a/src/mainboard/asrock/b75m-itx/acpi/ec.asl b/src/mainboard/asrock/b75m-itx/acpi/ec.asl
new file mode 100644
index 0000000000..16990d45f4
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/acpi/ec.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: CC-PDDC */
+
+/* Please update the license if adding licensable material. */
diff --git a/src/mainboard/asrock/b75m-itx/acpi/platform.asl b/src/mainboard/asrock/b75m-itx/acpi/platform.asl
new file mode 100644
index 0000000000..7b1b2b2975
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/acpi/platform.asl
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+Method(_WAK,1)
+{
+	Return(Package(){0,0})
+}
+
+Method(_PTS,1)
+{
+}
diff --git a/src/mainboard/asrock/b75m-itx/acpi/superio.asl b/src/mainboard/asrock/b75m-itx/acpi/superio.asl
new file mode 100644
index 0000000000..ee2eabeb75
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/acpi/superio.asl
@@ -0,0 +1,3 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <drivers/pc80/pc/ps2_controller.asl>
diff --git a/src/mainboard/asrock/b75m-itx/board_info.txt b/src/mainboard/asrock/b75m-itx/board_info.txt
new file mode 100644
index 0000000000..a3e84129da
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/board_info.txt
@@ -0,0 +1,7 @@
+Category: desktop
+Board URL: https://www.asrock.com/mb/Intel/B75M-ITX/
+ROM protocol: SPI
+Flashrom support: y
+ROM package: DIP-8
+ROM socketed: y
+Release year: 2012
diff --git a/src/mainboard/asrock/b75m-itx/cmos.default b/src/mainboard/asrock/b75m-itx/cmos.default
new file mode 100644
index 0000000000..23386fb6d3
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/cmos.default
@@ -0,0 +1,7 @@
+boot_option=Fallback
+debug_level=Debug
+nmi=Disable
+power_on_after_fail=Disable
+sata_mode=AHCI
+gfx_uma_size=64M
+cpu_fan_tach_src=CPU_FAN1
diff --git a/src/mainboard/asrock/b75m-itx/cmos.layout b/src/mainboard/asrock/b75m-itx/cmos.layout
new file mode 100644
index 0000000000..35b4d50c75
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/cmos.layout
@@ -0,0 +1,96 @@
+## SPDX-License-Identifier: GPL-2.0-or-later
+
+# -----------------------------------------------------------------
+entries
+
+# -----------------------------------------------------------------
+0	120	r	0	reserved_memory
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384	1	e	2	boot_option
+388	4	h	0	reboot_counter
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+395	4	e	3	debug_level
+
+# coreboot config options: southbridge
+408	1	e	1	nmi
+
+409	2	e	4	power_on_after_fail
+411	2	e	5	sata_mode
+
+# coreboot config options: northbridge
+416	5	e	6	gfx_uma_size
+
+# coreboot config options: mainboard-specific
+421	2	e	7	cpu_fan_tach_src
+
+# coreboot config options: check sums
+984	16	h	0	check_sum
+
+# -----------------------------------------------------------------
+
+enumerations
+#ID	value	text
+
+# Generic on/off enum
+1	0	Disable
+1	1	Enable
+
+# boot_option
+2	0	Fallback
+2	1	Normal
+
+# debug_level
+3	0	Emergency
+3	1	Alert
+3	2	Critical
+3	3	Error
+3	4	Warning
+3	5	Notice
+3	6	Info
+3	7	Debug
+3	8	Spew
+
+# power_on_after_fail
+4	0	Disable
+4	1	Enable
+4	2	Keep
+
+# sata_mode
+5	0	AHCI
+5	1	Compatible
+5	2	Legacy
+
+# gfx_uma_size (Intel IGP Video RAM size)
+6	0	32M
+6	1	64M
+6	2	96M
+6	3	128M
+6	4	160M
+6	5	192M
+6	6	224M
+6	7	256M
+6	8	288M
+6	9	320M
+6	10	352M
+6	11	384M
+6	12	416M
+6	13	448M
+6	14	480M
+6	15	512M
+6	16	1024M
+
+# cpu_fan_tach_src (select which header provides the tachometer
+# signal to the Super I/O on its CPUFANIN input)
+7	0	None
+7	1	CPU_FAN1
+7	2	CPU_FAN2
+7	3	Both
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 423 984
diff --git a/src/mainboard/asrock/b75m-itx/data.vbt b/src/mainboard/asrock/b75m-itx/data.vbt
new file mode 100644
index 0000000000..52a8268f33
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/data.vbt
diff --git a/src/mainboard/asrock/b75m-itx/devicetree.cb b/src/mainboard/asrock/b75m-itx/devicetree.cb
new file mode 100644
index 0000000000..9fdad959b1
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/devicetree.cb
@@ -0,0 +1,125 @@
+# SPDX-License-Identifier: GPL-2.0-or-later
+
+chip northbridge/intel/sandybridge
+	register "gpu_dp_b_hotplug" = "4"
+	register "gpu_dp_c_hotplug" = "4"
+	register "gpu_dp_d_hotplug" = "4"
+
+	device domain 0 on
+		device pci 00.0 on
+			subsystemid 0x1849 0x0150
+		end
+		device pci 01.0 on
+			subsystemid 0x1849 0x0151
+		end
+		device pci 02.0 on
+			subsystemid 0x1849 0x0152
+		end
+		chip southbridge/intel/bd82x6x
+			register "gen1_dec" = "0x000c0291"
+			register "gen2_dec" = "0x000c0241"
+			register "gen3_dec" = "0x000c0251"
+			register "sata_interface_speed_support" = "0x3"
+			register "sata_port_map" = "0x3f"
+			register "superspeed_capable_ports" = "0x0000000f"
+			register "xhci_overcurrent_mapping" = "0x00000c03"
+			register "xhci_switchable_ports" = "0x0000000f"
+			register "spi_uvscc" = "0x2005"
+			register "spi_lvscc" = "0x2005"
+
+			device pci 14.0 on  # USB 3.0 Controller
+				subsystemid 0x1849 0x1e31
+			end
+			device pci 16.0 on  # Management Engine Interface 1
+				subsystemid 0x1849 0x1e3a
+			end
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 on  # Management Engine KT
+				subsystemid 0x1849 0x1e3d
+			end
+			device pci 19.0 off end # Intel Gigabit Ethernet
+			device pci 1a.0 on  # USB2 EHCI #2
+				subsystemid 0x1849 0x1e2d
+			end
+			device pci 1b.0 on  # HDA Audio controller
+				subsystemid 0x1849 0x8892
+			end
+			device pci 1c.0 on  # PCIe Port #1
+				subsystemid 0x1849 0x1e10
+			end
+			device pci 1c.1 off end # PCIe Port #2
+			device pci 1c.2 off end # PCIe Port #3
+			device pci 1c.3 on  # PCIe Port #4
+				subsystemid 0x1849 0x1e16
+			end
+			device pci 1c.4 off end # PCIe Port #5
+			device pci 1c.5 on  # PCIe Port #6, Realtek PCIe GbE Controller
+				subsystemid 0x1849 0x1e1a
+			end
+			device pci 1c.6 off end # PCIe Port #7
+			device pci 1c.7 off end # PCIe Port #8
+			device pci 1d.0 on  # USB2 EHCI #1
+				subsystemid 0x1849 0x1e26
+			end
+			device pci 1e.0 off end # PCI bridge
+			device pci 1f.0 on  # LPC bridge
+				subsystemid 0x1849 0x1e49
+				chip superio/nuvoton/nct6776
+					device pnp 2e.0 off end		# Floppy
+					device pnp 2e.1 on		# Parallel port
+						# global
+						irq 0x1c = 0x80
+						irq 0x27 = 0xc0
+						irq 0x2a = 0x62
+						# parallel port
+						io 0x60 = 0x378
+						irq 0x70 = 5
+						drq 0x74 = 3
+					end
+					device pnp 2e.2 on		# COM1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.3 off end		# COM2, IR
+					device pnp 2e.5 on		# Keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 1
+						irq 0x72 = 12
+					end
+					device pnp 2e.6 off end		# CIR
+					device pnp 2e.7 off end		# GPIO6-9
+					device pnp 2e.8 off end		# WDT1, GPIO0, GPIO1, GPIOA
+					device pnp 2e.9 off end		# GPIO2-5
+					device pnp 2e.a on		# ACPI
+						irq 0xe0 = 0x01
+						irq 0xe3 = 0x14
+						irq 0xe4 = 0x10		# + enable 3VSBSW#
+						irq 0xe6 = 0x4c
+						irq 0xe9 = 0x02
+						irq 0xf0 = 0x20		# + pin 70 = 3VSBSW
+					end
+					device pnp 2e.b on		# HWM, front panel LED
+						irq 0x30 = 0xe1		# + Fan RPM sense pins
+						io  0x60 = 0x0290	# + HWM base address
+					end
+					device pnp 2e.d on end		# VID
+					device pnp 2e.e off end		# CIR WAKE-UP
+					device pnp 2e.f on end		# GPIO Push-Pull or Open-drain
+					device pnp 2e.14 on end		# SVID
+					device pnp 2e.16 on end		# Deep Sleep
+					device pnp 2e.17 on end		# GPIOA
+				end
+			end
+			device pci 1f.2 on  # SATA Controller 1
+				subsystemid 0x1849 0x1e02
+			end
+			device pci 1f.3 on  # SMBus
+				subsystemid 0x1849 0x1e22
+			end
+			device pci 1f.5 off end
+			device pci 1f.6 off end # Thermal
+		end
+	end
+end
diff --git a/src/mainboard/asrock/b75m-itx/dsdt.asl b/src/mainboard/asrock/b75m-itx/dsdt.asl
new file mode 100644
index 0000000000..bce1d9d937
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/dsdt.asl
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <acpi/acpi.h>
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	ACPI_DSDT_REV_2,
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20141018
+)
+{
+	#include <acpi/dsdt_top.asl>
+	#include "acpi/platform.asl"
+	#include <cpu/intel/common/acpi/cpu.asl>
+	#include <southbridge/intel/common/acpi/platform.asl>
+	#include <southbridge/intel/bd82x6x/acpi/globalnvs.asl>
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	Device (\_SB.PCI0) {
+		#include <northbridge/intel/sandybridge/acpi/sandybridge.asl>
+		#include <southbridge/intel/bd82x6x/acpi/pch.asl>
+	}
+}
diff --git a/src/mainboard/asrock/b75m-itx/early_init.c b/src/mainboard/asrock/b75m-itx/early_init.c
new file mode 100644
index 0000000000..189e24474a
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/early_init.c
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <bootblock_common.h>
+#include <northbridge/intel/sandybridge/raminit_native.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+const struct southbridge_usb_port mainboard_usb_ports[] = {
+	{1, 0, 0}, {1, 0, 0}, {1, 1, 1}, {1, 1, 1}, {1, 1, 2}, {1, 1, 2}, {1, 0, 3},
+	{1, 0, 3}, {1, 0, 4}, {1, 0, 4}, {1, 0, 6}, {1, 1, 5}, {1, 1, 5}, {1, 0, 6},
+};
+
+void mainboard_get_spd(spd_raw_data *spd, bool id_only)
+{
+	read_spd(&spd[0], 0x50, id_only);
+	read_spd(&spd[2], 0x52, id_only);
+}
diff --git a/src/mainboard/asrock/b75m-itx/gma-mainboard.ads b/src/mainboard/asrock/b75m-itx/gma-mainboard.ads
new file mode 100644
index 0000000000..3f217ca730
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/gma-mainboard.ads
@@ -0,0 +1,17 @@
+-- SPDX-License-Identifier: GPL-2.0-or-later
+
+with HW.GFX.GMA;
+with HW.GFX.GMA.Display_Probing;
+
+use HW.GFX.GMA;
+use HW.GFX.GMA.Display_Probing;
+
+private package GMA.Mainboard is
+
+   ports : constant Port_List :=
+     (HDMI1, -- mainboard DVI port
+      HDMI3, -- mainboard HDMI port
+      Analog,
+      others => Disabled);
+
+end GMA.Mainboard;
diff --git a/src/mainboard/asrock/b75m-itx/gpio.c b/src/mainboard/asrock/b75m-itx/gpio.c
new file mode 100644
index 0000000000..a063510dda
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/gpio.c
@@ -0,0 +1,170 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <southbridge/intel/common/gpio.h>
+
+static const struct pch_gpio_set1 pch_gpio_set1_mode = {
+	.gpio0 = GPIO_MODE_GPIO,
+	.gpio1 = GPIO_MODE_GPIO,
+	.gpio2 = GPIO_MODE_NATIVE,
+	.gpio3 = GPIO_MODE_NATIVE,
+	.gpio4 = GPIO_MODE_NATIVE,
+	.gpio5 = GPIO_MODE_NATIVE,
+	.gpio6 = GPIO_MODE_GPIO,
+	.gpio7 = GPIO_MODE_GPIO,
+	.gpio8 = GPIO_MODE_GPIO,
+	.gpio9 = GPIO_MODE_NATIVE,
+	.gpio10 = GPIO_MODE_NATIVE,
+	.gpio11 = GPIO_MODE_NATIVE,
+	.gpio12 = GPIO_MODE_GPIO,
+	.gpio13 = GPIO_MODE_GPIO,
+	.gpio14 = GPIO_MODE_NATIVE,
+	.gpio15 = GPIO_MODE_GPIO,
+	.gpio16 = GPIO_MODE_GPIO,
+	.gpio17 = GPIO_MODE_GPIO,
+	.gpio18 = GPIO_MODE_NATIVE,
+	.gpio19 = GPIO_MODE_NATIVE,
+	.gpio20 = GPIO_MODE_NATIVE,
+	.gpio21 = GPIO_MODE_NATIVE,
+	.gpio22 = GPIO_MODE_NATIVE,
+	.gpio23 = GPIO_MODE_NATIVE,
+	.gpio24 = GPIO_MODE_GPIO,
+	.gpio25 = GPIO_MODE_NATIVE,
+	.gpio26 = GPIO_MODE_NATIVE,
+	.gpio27 = GPIO_MODE_GPIO,
+	.gpio28 = GPIO_MODE_GPIO,
+	.gpio29 = GPIO_MODE_GPIO,
+	.gpio30 = GPIO_MODE_NATIVE,
+	.gpio31 = GPIO_MODE_GPIO,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_direction = {
+	.gpio0 = GPIO_DIR_INPUT,
+	.gpio1 = GPIO_DIR_INPUT,
+	.gpio6 = GPIO_DIR_INPUT,
+	.gpio7 = GPIO_DIR_INPUT,
+	.gpio8 = GPIO_DIR_INPUT,
+	.gpio12 = GPIO_DIR_OUTPUT,
+	.gpio13 = GPIO_DIR_INPUT,
+	.gpio15 = GPIO_DIR_OUTPUT,
+	.gpio16 = GPIO_DIR_INPUT,
+	.gpio17 = GPIO_DIR_INPUT,
+	.gpio24 = GPIO_DIR_OUTPUT,
+	.gpio27 = GPIO_DIR_INPUT,
+	.gpio28 = GPIO_DIR_OUTPUT,
+	.gpio29 = GPIO_DIR_OUTPUT,
+	.gpio31 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_level = {
+	.gpio12 = GPIO_LEVEL_HIGH,
+	.gpio15 = GPIO_LEVEL_LOW,
+	.gpio24 = GPIO_LEVEL_LOW,
+	.gpio28 = GPIO_LEVEL_LOW,
+	.gpio29 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_reset = {};
+
+static const struct pch_gpio_set1 pch_gpio_set1_invert = {
+	.gpio13 = GPIO_INVERT,
+};
+
+static const struct pch_gpio_set1 pch_gpio_set1_blink = {};
+
+static const struct pch_gpio_set2 pch_gpio_set2_mode = {
+	.gpio32 = GPIO_MODE_GPIO,
+	.gpio33 = GPIO_MODE_GPIO,
+	.gpio34 = GPIO_MODE_GPIO,
+	.gpio35 = GPIO_MODE_NATIVE,
+	.gpio36 = GPIO_MODE_NATIVE,
+	.gpio37 = GPIO_MODE_NATIVE,
+	.gpio38 = GPIO_MODE_NATIVE,
+	.gpio39 = GPIO_MODE_NATIVE,
+	.gpio40 = GPIO_MODE_NATIVE,
+	.gpio41 = GPIO_MODE_NATIVE,
+	.gpio42 = GPIO_MODE_NATIVE,
+	.gpio43 = GPIO_MODE_NATIVE,
+	.gpio44 = GPIO_MODE_NATIVE,
+	.gpio45 = GPIO_MODE_NATIVE,
+	.gpio46 = GPIO_MODE_NATIVE,
+	.gpio47 = GPIO_MODE_NATIVE,
+	.gpio48 = GPIO_MODE_NATIVE,
+	.gpio49 = GPIO_MODE_GPIO,
+	.gpio50 = GPIO_MODE_NATIVE,
+	.gpio51 = GPIO_MODE_NATIVE,
+	.gpio52 = GPIO_MODE_NATIVE,
+	.gpio53 = GPIO_MODE_NATIVE,
+	.gpio54 = GPIO_MODE_NATIVE,
+	.gpio55 = GPIO_MODE_NATIVE,
+	.gpio56 = GPIO_MODE_NATIVE,
+	.gpio57 = GPIO_MODE_GPIO,
+	.gpio58 = GPIO_MODE_NATIVE,
+	.gpio59 = GPIO_MODE_NATIVE,
+	.gpio60 = GPIO_MODE_NATIVE,
+	.gpio61 = GPIO_MODE_NATIVE,
+	.gpio62 = GPIO_MODE_NATIVE,
+	.gpio63 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_direction = {
+	.gpio32 = GPIO_DIR_OUTPUT,
+	.gpio33 = GPIO_DIR_OUTPUT,
+	.gpio34 = GPIO_DIR_INPUT,
+	.gpio49 = GPIO_DIR_INPUT,
+	.gpio57 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_level = {
+	.gpio32 = GPIO_LEVEL_HIGH,
+	.gpio33 = GPIO_LEVEL_HIGH,
+};
+
+static const struct pch_gpio_set2 pch_gpio_set2_reset = {};
+
+static const struct pch_gpio_set3 pch_gpio_set3_mode = {
+	.gpio64 = GPIO_MODE_NATIVE,
+	.gpio65 = GPIO_MODE_NATIVE,
+	.gpio66 = GPIO_MODE_NATIVE,
+	.gpio67 = GPIO_MODE_NATIVE,
+	.gpio68 = GPIO_MODE_GPIO,
+	.gpio69 = GPIO_MODE_GPIO,
+	.gpio70 = GPIO_MODE_NATIVE,
+	.gpio71 = GPIO_MODE_NATIVE,
+	.gpio72 = GPIO_MODE_GPIO,
+	.gpio73 = GPIO_MODE_NATIVE,
+	.gpio74 = GPIO_MODE_NATIVE,
+	.gpio75 = GPIO_MODE_NATIVE,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_direction = {
+	.gpio68 = GPIO_DIR_INPUT,
+	.gpio69 = GPIO_DIR_INPUT,
+	.gpio72 = GPIO_DIR_INPUT,
+};
+
+static const struct pch_gpio_set3 pch_gpio_set3_level = {};
+
+static const struct pch_gpio_set3 pch_gpio_set3_reset = {};
+
+const struct pch_gpio_map mainboard_gpio_map = {
+	.set1 = {
+			.mode = &pch_gpio_set1_mode,
+			.direction = &pch_gpio_set1_direction,
+			.level = &pch_gpio_set1_level,
+			.blink = &pch_gpio_set1_blink,
+			.invert = &pch_gpio_set1_invert,
+			.reset = &pch_gpio_set1_reset,
+	},
+	.set2 = {
+			.mode = &pch_gpio_set2_mode,
+			.direction = &pch_gpio_set2_direction,
+			.level = &pch_gpio_set2_level,
+			.reset = &pch_gpio_set2_reset,
+	},
+	.set3 = {
+			.mode = &pch_gpio_set3_mode,
+			.direction = &pch_gpio_set3_direction,
+			.level = &pch_gpio_set3_level,
+			.reset = &pch_gpio_set3_reset,
+	},
+};
diff --git a/src/mainboard/asrock/b75m-itx/hda_verb.c b/src/mainboard/asrock/b75m-itx/hda_verb.c
new file mode 100644
index 0000000000..d2824afcbe
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/hda_verb.c
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/azalia_device.h>
+
+const u32 cim_verb_data[] = {
+	0x10ec0892, /* Codec Vendor / Device ID: Realtek */
+	0x18498892, /* Subsystem ID */
+	15,	    /* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(0, 0x18498892),
+	AZALIA_PIN_CFG(0, 0x11, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x12, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x14, 0x01014010),
+	AZALIA_PIN_CFG(0, 0x15, 0x01011012),
+	AZALIA_PIN_CFG(0, 0x16, 0x01016011),
+	AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x18, 0x01a19840),
+	AZALIA_PIN_CFG(0, 0x19, 0x02a19c60),
+	AZALIA_PIN_CFG(0, 0x1a, 0x0181304f),
+	AZALIA_PIN_CFG(0, 0x1b, 0x02214c20),
+	AZALIA_PIN_CFG(0, 0x1c, 0x411111f0),
+	AZALIA_PIN_CFG(0, 0x1d, 0x4005e601),
+	AZALIA_PIN_CFG(0, 0x1e, 0x01452130),
+	AZALIA_PIN_CFG(0, 0x1f, 0x411111f0),
+
+	0x80862806, /* Codec Vendor / Device ID: Intel */
+	0x80860101, /* Subsystem ID */
+	4,	    /* Number of 4 dword sets */
+	AZALIA_SUBVENDOR(3, 0x80860101),
+	AZALIA_PIN_CFG(3, 0x05, 0x18560010),
+	AZALIA_PIN_CFG(3, 0x06, 0x18560020),
+	AZALIA_PIN_CFG(3, 0x07, 0x18560030),
+};
+
+const u32 pc_beep_verbs[0] = {};
+
+AZALIA_ARRAY_SIZES;
diff --git a/src/mainboard/asrock/b75m-itx/mainboard.c b/src/mainboard/asrock/b75m-itx/mainboard.c
new file mode 100644
index 0000000000..472eb78f12
--- /dev/null
+++ b/src/mainboard/asrock/b75m-itx/mainboard.c
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+
+#include <device/device.h>
+#include <drivers/intel/gma/int15.h>
+#include <southbridge/intel/bd82x6x/pch.h>
+
+static void mainboard_enable(struct device *dev)
+{
+	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_NONE, GMA_INT15_PANEL_FIT_DEFAULT,
+					GMA_INT15_BOOT_DISPLAY_CRT, 0);
+}
+
+struct chip_operations mainboard_ops = {
+	.enable_dev = mainboard_enable,
+};