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-rw-r--r--src/mainboard/a-trend/atc-6220/auto.c5
-rw-r--r--src/mainboard/a-trend/atc-6240/auto.c5
-rw-r--r--src/mainboard/abit/be6-ii_v2_0/auto.c5
-rw-r--r--src/mainboard/asus/p2b-d/auto.c5
-rw-r--r--src/mainboard/asus/p2b-ds/auto.c5
-rw-r--r--src/mainboard/asus/p2b-f/auto.c5
-rw-r--r--src/mainboard/asus/p2b/auto.c5
-rw-r--r--src/mainboard/asus/p3b-f/auto.c5
-rw-r--r--src/mainboard/azza/pt-6ibd/auto.c5
-rw-r--r--src/mainboard/biostar/m6tba/auto.c5
-rw-r--r--src/mainboard/compaq/deskpro_en_sff_p600/auto.c5
-rw-r--r--src/mainboard/gigabyte/ga-6bxc/auto.c5
-rw-r--r--src/mainboard/msi/ms6119/auto.c5
-rw-r--r--src/mainboard/msi/ms6147/auto.c5
-rw-r--r--src/mainboard/soyo/sy-6ba-plus-iii/auto.c5
-rw-r--r--src/mainboard/tyan/s1846/auto.c5
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb_enable_rom.c35
-rw-r--r--src/southbridge/intel/i82371eb/i82371eb_isa.c8
18 files changed, 115 insertions, 8 deletions
diff --git a/src/mainboard/a-trend/atc-6220/auto.c b/src/mainboard/a-trend/atc-6220/auto.c
index fa027e1127..85e5f47cc7 100644
--- a/src/mainboard/a-trend/atc-6220/auto.c
+++ b/src/mainboard/a-trend/atc-6220/auto.c
@@ -30,6 +30,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
enable_smbus();
/* dump_spd_registers(); */
sdram_set_registers();
diff --git a/src/mainboard/a-trend/atc-6240/auto.c b/src/mainboard/a-trend/atc-6240/auto.c
index 756d0e0709..cd07998807 100644
--- a/src/mainboard/a-trend/atc-6240/auto.c
+++ b/src/mainboard/a-trend/atc-6240/auto.c
@@ -30,6 +30,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
enable_smbus();
/* dump_spd_registers(); */
sdram_set_registers();
diff --git a/src/mainboard/abit/be6-ii_v2_0/auto.c b/src/mainboard/abit/be6-ii_v2_0/auto.c
index 70beca92ac..7d323821ff 100644
--- a/src/mainboard/abit/be6-ii_v2_0/auto.c
+++ b/src/mainboard/abit/be6-ii_v2_0/auto.c
@@ -30,6 +30,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge at 00:07.0. */
+
enable_smbus();
/* dump_spd_registers(); */
sdram_set_registers();
diff --git a/src/mainboard/asus/p2b-d/auto.c b/src/mainboard/asus/p2b-d/auto.c
index 4857cd540f..7371ba7870 100644
--- a/src/mainboard/asus/p2b-d/auto.c
+++ b/src/mainboard/asus/p2b-d/auto.c
@@ -31,6 +31,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
enable_smbus();
/* dump_spd_registers(); */
sdram_set_registers();
diff --git a/src/mainboard/asus/p2b-ds/auto.c b/src/mainboard/asus/p2b-ds/auto.c
index 141f444684..810d7e352b 100644
--- a/src/mainboard/asus/p2b-ds/auto.c
+++ b/src/mainboard/asus/p2b-ds/auto.c
@@ -31,6 +31,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
enable_smbus();
/* dump_spd_registers(); */
sdram_set_registers();
diff --git a/src/mainboard/asus/p2b-f/auto.c b/src/mainboard/asus/p2b-f/auto.c
index 86b0759949..76d14ae15d 100644
--- a/src/mainboard/asus/p2b-f/auto.c
+++ b/src/mainboard/asus/p2b-f/auto.c
@@ -30,6 +30,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
enable_smbus();
/* dump_spd_registers(); */
sdram_set_registers();
diff --git a/src/mainboard/asus/p2b/auto.c b/src/mainboard/asus/p2b/auto.c
index fa027e1127..2dfdb2432f 100644
--- a/src/mainboard/asus/p2b/auto.c
+++ b/src/mainboard/asus/p2b/auto.c
@@ -30,6 +30,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge at 00:04.0. */
+
enable_smbus();
/* dump_spd_registers(); */
sdram_set_registers();
diff --git a/src/mainboard/asus/p3b-f/auto.c b/src/mainboard/asus/p3b-f/auto.c
index c9c64fc8e5..fb3169f8ad 100644
--- a/src/mainboard/asus/p3b-f/auto.c
+++ b/src/mainboard/asus/p3b-f/auto.c
@@ -30,6 +30,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 4, 0)); /* ISA bridge is 00:04.0. */
+
enable_smbus();
/* dump_spd_registers(); */
sdram_set_registers();
diff --git a/src/mainboard/azza/pt-6ibd/auto.c b/src/mainboard/azza/pt-6ibd/auto.c
index 65a7fcc1f9..b2b323b30f 100644
--- a/src/mainboard/azza/pt-6ibd/auto.c
+++ b/src/mainboard/azza/pt-6ibd/auto.c
@@ -30,6 +30,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
enable_smbus();
/* dump_spd_registers(); */
sdram_set_registers();
diff --git a/src/mainboard/biostar/m6tba/auto.c b/src/mainboard/biostar/m6tba/auto.c
index 4e018bd5b6..b956d3cb99 100644
--- a/src/mainboard/biostar/m6tba/auto.c
+++ b/src/mainboard/biostar/m6tba/auto.c
@@ -30,6 +30,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -59,6 +60,10 @@ static void main(unsigned long bist)
console_init();
report_bist_failure(bist);
enable_smbus();
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
/* dump_spd_registers(); */
sdram_set_registers();
sdram_set_spd_registers();
diff --git a/src/mainboard/compaq/deskpro_en_sff_p600/auto.c b/src/mainboard/compaq/deskpro_en_sff_p600/auto.c
index 238231e8c5..dee0ad418f 100644
--- a/src/mainboard/compaq/deskpro_en_sff_p600/auto.c
+++ b/src/mainboard/compaq/deskpro_en_sff_p600/auto.c
@@ -30,6 +30,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -61,6 +62,10 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 14, 0)); /* ISA bridge is 00:14.0. */
+
enable_smbus();
/* dump_spd_registers(); */
sdram_set_registers();
diff --git a/src/mainboard/gigabyte/ga-6bxc/auto.c b/src/mainboard/gigabyte/ga-6bxc/auto.c
index 79662ad577..e12daacd9e 100644
--- a/src/mainboard/gigabyte/ga-6bxc/auto.c
+++ b/src/mainboard/gigabyte/ga-6bxc/auto.c
@@ -30,6 +30,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
enable_smbus();
/* dump_spd_registers(); */
sdram_set_registers();
diff --git a/src/mainboard/msi/ms6119/auto.c b/src/mainboard/msi/ms6119/auto.c
index 899b3bc601..5d8cdd13ad 100644
--- a/src/mainboard/msi/ms6119/auto.c
+++ b/src/mainboard/msi/ms6119/auto.c
@@ -30,6 +30,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
enable_smbus();
/* dump_spd_registers(); */
sdram_set_registers();
diff --git a/src/mainboard/msi/ms6147/auto.c b/src/mainboard/msi/ms6147/auto.c
index 30398bef72..a9616c4f4e 100644
--- a/src/mainboard/msi/ms6147/auto.c
+++ b/src/mainboard/msi/ms6147/auto.c
@@ -30,6 +30,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
enable_smbus();
/* dump_spd_registers(); */
sdram_set_registers();
diff --git a/src/mainboard/soyo/sy-6ba-plus-iii/auto.c b/src/mainboard/soyo/sy-6ba-plus-iii/auto.c
index 81241ac553..72c5f58831 100644
--- a/src/mainboard/soyo/sy-6ba-plus-iii/auto.c
+++ b/src/mainboard/soyo/sy-6ba-plus-iii/auto.c
@@ -30,6 +30,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
enable_smbus();
/* dump_spd_registers(); */
sdram_set_registers();
diff --git a/src/mainboard/tyan/s1846/auto.c b/src/mainboard/tyan/s1846/auto.c
index 68eca0eeda..64af692349 100644
--- a/src/mainboard/tyan/s1846/auto.c
+++ b/src/mainboard/tyan/s1846/auto.c
@@ -30,6 +30,7 @@
#include "pc80/serial.c"
#include "arch/i386/lib/console.c"
#include "lib/ramtest.c"
+#include "southbridge/intel/i82371eb/i82371eb_enable_rom.c"
#include "southbridge/intel/i82371eb/i82371eb_early_smbus.c"
#include "northbridge/intel/i440bx/raminit.h"
#include "lib/debug.c"
@@ -58,6 +59,10 @@ static void main(unsigned long bist)
uart_init();
console_init();
report_bist_failure(bist);
+
+ /* Enable access to the full ROM chip, needed very early by CBFS. */
+ i82371eb_enable_rom(PCI_DEV(0, 7, 0)); /* ISA bridge is 00:07.0. */
+
enable_smbus();
/* dump_spd_registers(); */
sdram_set_registers();
diff --git a/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c b/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c
new file mode 100644
index 0000000000..5b12e462be
--- /dev/null
+++ b/src/southbridge/intel/i82371eb/i82371eb_enable_rom.c
@@ -0,0 +1,35 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include "i82371eb.h"
+
+static void i82371eb_enable_rom(device_t dev)
+{
+ u16 reg16;
+
+ /* Enable access to the whole ROM, disable ROM write access. */
+ reg16 = pci_read_config16(dev, XBCS);
+ reg16 |= LOWER_BIOS_ENABLE;
+ reg16 |= EXT_BIOS_ENABLE;
+ reg16 |= EXT_BIOS_ENABLE_1MB;
+ reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */
+ pci_write_config16(dev, XBCS, reg16);
+}
diff --git a/src/southbridge/intel/i82371eb/i82371eb_isa.c b/src/southbridge/intel/i82371eb/i82371eb_isa.c
index a521d86bb0..6a8de8d80e 100644
--- a/src/southbridge/intel/i82371eb/i82371eb_isa.c
+++ b/src/southbridge/intel/i82371eb/i82371eb_isa.c
@@ -35,14 +35,6 @@ static void isa_init(struct device *dev)
/* Initialize the real time clock (RTC). */
rtc_init(0);
- /* Enable access to all BIOS regions. */
- reg16 = pci_read_config16(dev, XBCS);
- reg16 |= LOWER_BIOS_ENABLE;
- reg16 |= EXT_BIOS_ENABLE;
- reg16 |= EXT_BIOS_ENABLE_1MB;
- reg16 &= ~(WRITE_PROTECT_ENABLE); /* Disable ROM write access. */
- pci_write_config16(dev, XBCS, reg16);
-
/*
* The PIIX4 can support the full ISA bus, or the Extended I/O (EIO)
* bus, which is a subset of ISA. We select the full ISA bus here.
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-10 10:30:39 +0000