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-rw-r--r--src/northbridge/intel/sandybridge/mchbar_regs.h12
-rw-r--r--src/northbridge/intel/sandybridge/raminit_common.c16
2 files changed, 14 insertions, 14 deletions
diff --git a/src/northbridge/intel/sandybridge/mchbar_regs.h b/src/northbridge/intel/sandybridge/mchbar_regs.h
index 74377b247b..286b55657f 100644
--- a/src/northbridge/intel/sandybridge/mchbar_regs.h
+++ b/src/northbridge/intel/sandybridge/mchbar_regs.h
@@ -209,6 +209,12 @@
#define CRCOMPOFST2 0x3714 /* CMD DRV, SComp and Static Leg controls */
+/*
+ * The register bank that would correspond to Channel 3 are actually "broadcast" registers.
+ * They can be used to write values to all channels. Use this macro instead of a literal '3'.
+ */
+#define BROADCAST_CH 3
+
/* MC per-channel registers */
#define TC_DBP_ch(ch) Cx(0x4000, ch) /* Timings: BIN */
#define TC_RAP_ch(ch) Cx(0x4004, ch) /* Timings: Regular access */
@@ -315,12 +321,6 @@
#define IOSAV_By_BW_SERROR_C(y) Ly(0x4d40, y) /* IOSAV Bytelane Bit-wise error */
-#define IOSAV_n_SP_CMD_ADDR(n) Ly(0x4e00, n) /* Sub-sequence special command address */
-#define IOSAV_n_ADDR_UPDATE(n) Ly(0x4e10, n) /* Address update after command execution */
-#define IOSAV_n_SP_CMD_CTRL(n) Ly(0x4e20, n) /* Command signals in sub-sequence command */
-#define IOSAV_n_SUBSEQ_CTRL(n) Ly(0x4e30, n) /* Sub-sequence command parameter control */
-#define IOSAV_n_ADDRESS_LFSR(n) Ly(0x4e40, n) /* 23-bit LFSR value of the sequence */
-
#define PM_THML_STAT 0x4e80 /* Thermal status of each rank */
#define IOSAV_SEQ_CTL 0x4e84 /* IOSAV sequence level control */
#define IOSAV_DATA_CTL 0x4e88 /* Data control in IOSAV mode */
diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c
index 05cffd3fd8..ab3386bebb 100644
--- a/src/northbridge/intel/sandybridge/raminit_common.c
+++ b/src/northbridge/intel/sandybridge/raminit_common.c
@@ -808,16 +808,16 @@ void dram_mrscommands(ramctr_timing *ctrl)
}
/* DRAM command NOP (without ODT nor chip selects) */
- MCHBAR32(IOSAV_n_SP_CMD_CTRL(0)) = IOSAV_NOP & NO_RANKSEL & ~(0xff << 8);
- MCHBAR32(IOSAV_n_SUBSEQ_CTRL(0)) = 0xf1001;
- MCHBAR32(IOSAV_n_SP_CMD_ADDR(0)) = 0x60002;
- MCHBAR32(IOSAV_n_ADDR_UPDATE(0)) = 0;
+ MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(BROADCAST_CH, 0)) = IOSAV_NOP & NO_RANKSEL & ~(0xff << 8);
+ MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(BROADCAST_CH, 0)) = 0xf1001;
+ MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(BROADCAST_CH, 0)) = 0x60002;
+ MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(BROADCAST_CH, 0)) = 0;
/* DRAM command ZQCL */
- MCHBAR32(IOSAV_n_SP_CMD_CTRL(1)) = IOSAV_ZQCS;
- MCHBAR32(IOSAV_n_SUBSEQ_CTRL(1)) = 0x1901001;
- MCHBAR32(IOSAV_n_SP_CMD_ADDR(1)) = 0x60400;
- MCHBAR32(IOSAV_n_ADDR_UPDATE(1)) = 0x288;
+ MCHBAR32(IOSAV_n_SP_CMD_CTRL_ch(BROADCAST_CH, 1)) = IOSAV_ZQCS;
+ MCHBAR32(IOSAV_n_SUBSEQ_CTRL_ch(BROADCAST_CH, 1)) = 0x1901001;
+ MCHBAR32(IOSAV_n_SP_CMD_ADDR_ch(BROADCAST_CH, 1)) = 0x60400;
+ MCHBAR32(IOSAV_n_ADDR_UPDATE_ch(BROADCAST_CH, 1)) = 0x288;
/* Execute command queue on all channels. Do it four times. */
MCHBAR32(IOSAV_SEQ_CTL) = (1 << 18) | 4;