diff options
62 files changed, 189 insertions, 200 deletions
diff --git a/src/mainboard/amd/parmer/buildOpts.c b/src/mainboard/amd/parmer/buildOpts.c index 030634605d..319c811042 100644 --- a/src/mainboard/amd/parmer/buildOpts.c +++ b/src/mainboard/amd/parmer/buildOpts.c @@ -47,7 +47,7 @@ #include "cpuLateInit.h" #include "GnbInterface.h" -GPIO_CONTROL parmer_gpio[] = { +CONST GPIO_CONTROL parmer_gpio[] = { {183, Function1, GpioIn | GpioOutEnB | PullUpB}, {-1} }; diff --git a/src/mainboard/amd/thatcher/buildOpts.c b/src/mainboard/amd/thatcher/buildOpts.c index 72390c0ae2..5f21d2e2f9 100644 --- a/src/mainboard/amd/thatcher/buildOpts.c +++ b/src/mainboard/amd/thatcher/buildOpts.c @@ -49,7 +49,7 @@ #define FCH_NO_XHCI_SUPPORT TRUE -GPIO_CONTROL thatcher_gpio[] = { +CONST GPIO_CONTROL thatcher_gpio[] = { {183, Function1, PullUpB}, {-1} }; diff --git a/src/mainboard/asus/a88xm-e/buildOpts.c b/src/mainboard/asus/a88xm-e/buildOpts.c index 25e7d3aed2..363e31f96d 100644 --- a/src/mainboard/asus/a88xm-e/buildOpts.c +++ b/src/mainboard/asus/a88xm-e/buildOpts.c @@ -54,7 +54,7 @@ #define BLDCFG_FCH_GPP_PORT1_PRESENT TRUE #define BLDCFG_FCH_GPP_PORT2_PRESENT TRUE -GPIO_CONTROL a88xm_e_gpio[] = { +CONST GPIO_CONTROL a88xm_e_gpio[] = { {-1} }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (a88xm_e_gpio) diff --git a/src/mainboard/asus/f2a85-m/buildOpts.c b/src/mainboard/asus/f2a85-m/buildOpts.c index a69614fd47..b7e9c1b76a 100644 --- a/src/mainboard/asus/f2a85-m/buildOpts.c +++ b/src/mainboard/asus/f2a85-m/buildOpts.c @@ -53,7 +53,7 @@ #define BLDCFG_FCH_GPP_PORT1_PRESENT TRUE #define BLDCFG_FCH_GPP_PORT2_PRESENT CONFIG(BOARD_ASUS_F2A85_M_PRO) -GPIO_CONTROL f2a85_m_gpio[] = { +CONST GPIO_CONTROL f2a85_m_gpio[] = { {-1} }; #define BLDCFG_FCH_GPIO_CONTROL_LIST (f2a85_m_gpio) diff --git a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c index a3553c0dc7..377e39016b 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/buildOpts.c @@ -71,7 +71,7 @@ #define PULL_DOWN (PullDown | PullUpB) #define PULL_NONE (PullUpB) -GPIO_CONTROL pavilion_m6_1035dx_gpio[] = { +CONST GPIO_CONTROL pavilion_m6_1035dx_gpio[] = { {57, Function1, OUTPUT_HIGH | PULL_NONE}, /* WLAN enable */ {-1} }; @@ -87,7 +87,7 @@ GPIO_CONTROL pavilion_m6_1035dx_gpio[] = { #define SCI_MAP_XHCI_10_0 0x78 #define SCI_MAP_PWRBTN 0x73 -SCI_MAP_CONTROL m6_1035dx_sci_map[] = { +CONST SCI_MAP_CONTROL m6_1035dx_sci_map[] = { {GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE}, {GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE}, {GEVENT_PIN(PCIE_GEVENT), PCIE_GPE}, diff --git a/src/mainboard/lenovo/g505s/buildOpts.c b/src/mainboard/lenovo/g505s/buildOpts.c index 19add3ac9b..3bf316e4fd 100644 --- a/src/mainboard/lenovo/g505s/buildOpts.c +++ b/src/mainboard/lenovo/g505s/buildOpts.c @@ -71,7 +71,7 @@ #define PULL_DOWN (PullDown | PullUpB) #define PULL_NONE (PullUpB) -GPIO_CONTROL lenovo_g505s_gpio[] = { +CONST GPIO_CONTROL lenovo_g505s_gpio[] = { {57, Function1, OUTPUT_HIGH | PULL_NONE}, /* WLAN enable */ {-1} }; @@ -87,7 +87,7 @@ GPIO_CONTROL lenovo_g505s_gpio[] = { #define SCI_MAP_XHCI_10_0 0x78 #define SCI_MAP_PWRBTN 0x73 -SCI_MAP_CONTROL lenovo_g505s_sci_map[] = { +CONST SCI_MAP_CONTROL lenovo_g505s_sci_map[] = { {GEVENT_PIN(EC_SCI_GEVENT), EC_SCI_GPE}, {GEVENT_PIN(EC_LID_GEVENT), EC_LID_GPE}, {GEVENT_PIN(PCIE_GEVENT), PCIE_GPE}, diff --git a/src/mainboard/msi/ms7721/buildOpts.c b/src/mainboard/msi/ms7721/buildOpts.c index 3a0ac1c3eb..dd5f8940d9 100644 --- a/src/mainboard/msi/ms7721/buildOpts.c +++ b/src/mainboard/msi/ms7721/buildOpts.c @@ -52,7 +52,7 @@ #define BLDCFG_FCH_GPP_PORT0_PRESENT TRUE #define BLDCFG_FCH_GPP_PORT1_PRESENT TRUE -GPIO_CONTROL ms7721_m_gpio[] = { +CONST GPIO_CONTROL ms7721_m_gpio[] = { {-1} }; diff --git a/src/northbridge/amd/agesa/family15tn/Kconfig b/src/northbridge/amd/agesa/family15tn/Kconfig index 5bb7cca300..e3a5cc64d0 100644 --- a/src/northbridge/amd/agesa/family15tn/Kconfig +++ b/src/northbridge/amd/agesa/family15tn/Kconfig @@ -17,4 +17,7 @@ config ECAM_MMCONF_BASE_ADDRESS config ECAM_MMCONF_BUS_NUMBER default 64 +config AGESA_BROKEN_DATA_SECTION + default n + endif # NORTHBRIDGE_AMD_AGESA_FAMILY15_TN diff --git a/src/vendorcode/amd/agesa/common/amdlib.c b/src/vendorcode/amd/agesa/common/amdlib.c index 1f52fe0de5..dbfdce877e 100644 --- a/src/vendorcode/amd/agesa/common/amdlib.c +++ b/src/vendorcode/amd/agesa/common/amdlib.c @@ -375,7 +375,7 @@ LibAmdMsrRead ( VOID LibAmdMsrWrite ( IN UINT32 MsrAddress, - IN UINT64 *Value, + CONST IN UINT64 *Value, IN OUT AMD_CONFIG_PARAMS *ConfigPtr ) { diff --git a/src/vendorcode/amd/agesa/common/amdlib.h b/src/vendorcode/amd/agesa/common/amdlib.h index f5da2286b1..5ba39522b2 100644 --- a/src/vendorcode/amd/agesa/common/amdlib.h +++ b/src/vendorcode/amd/agesa/common/amdlib.h @@ -145,7 +145,7 @@ LibAmdMsrRead ( VOID LibAmdMsrWrite ( IN UINT32 MsrAddress, - IN UINT64 *Value, + CONST IN UINT64 *Value, IN OUT AMD_CONFIG_PARAMS *StdHeader ); diff --git a/src/vendorcode/amd/agesa/f15tn/AGESA.h b/src/vendorcode/amd/agesa/f15tn/AGESA.h index d41a5eec77..bf41f691d5 100644 --- a/src/vendorcode/amd/agesa/f15tn/AGESA.h +++ b/src/vendorcode/amd/agesa/f15tn/AGESA.h @@ -2734,9 +2734,9 @@ typedef struct { ///< [4] - IR Open Drain ///< [5] - IR Enable LED IN SD_CLOCK_CONTROL CfgFchSdClockControl; ///< FCH SD Clock Control - IN SCI_MAP_CONTROL *CfgFchSciMapControl; ///< FCH SCI Mapping Control + CONST IN SCI_MAP_CONTROL *CfgFchSciMapControl; ///< FCH SCI Mapping Control IN SATA_PHY_CONTROL *CfgFchSataPhyControl; ///< FCH SATA PHY Control - IN GPIO_CONTROL *CfgFchGpioControl; ///< FCH GPIO Control + CONST IN GPIO_CONTROL *CfgFchGpioControl; ///< FCH GPIO Control } FCH_PLATFORM_POLICY; @@ -2872,7 +2872,7 @@ typedef struct { ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM} IN UINT16 CfgLvdsSpreadSpectrumRate; ///< Lvds Spread Spectrum Rate ///< Build-time customizable only - @BldCfgItem{BLDCFG_GFX_LVDS_SPREAD_SPECTRUM_RATE} - IN FCH_PLATFORM_POLICY *FchBldCfg; ///< FCH platform build configuration policy + CONST IN FCH_PLATFORM_POLICY *FchBldCfg; ///< FCH platform build configuration policy IN BOOLEAN CfgIommuSupport; ///< IOMMU support IN UINT8 CfgLvdsPowerOnSeqDigonToDe; ///< Panel initialization timing diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionCpuFeaturesInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionCpuFeaturesInstall.h index 50829bdbde..c8f520750c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/OptionCpuFeaturesInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionCpuFeaturesInstall.h @@ -58,7 +58,7 @@ #include "OptionHtcInstall.h" #include "OptionPreserveMailboxInstall.h" -CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] = +CONST CPU_FEATURE_DESCRIPTOR* ROMDATA CONST SupportedCpuFeatureList[] = { OPTION_HW_C1E_FEAT OPTION_MSG_BASED_C1E_FEAT diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h index bd00756c43..977c82c57e 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionFamily15hInstall.h @@ -552,7 +552,7 @@ extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled; #if USES_REGISTER_TABLES == TRUE - CONST REGISTER_TABLE ROMDATA *F15TnRegisterTables[] = + CONST REGISTER_TABLE ROMDATA * CONST F15TnRegisterTables[] = { #if BASE_FAMILY_PCI == TRUE &F15PciRegisterTable, @@ -757,7 +757,7 @@ extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled; (PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert, #endif #if USES_REGISTER_TABLES == TRUE - (REGISTER_TABLE **) F15TnRegisterTables, + (CONST REGISTER_TABLE **) F15TnRegisterTables, #else NULL, #endif @@ -814,7 +814,7 @@ extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled; #endif - CONST UINT8 ROMDATA *CpuF15TnMicroCodePatchArray[] = + CONST UINT8 ROMDATA * CONST CpuF15TnMicroCodePatchArray[] = { F15_TN_UCODE_10F F15_TN_UCODE_0E diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h index 5ea5fd1595..156d1d27a4 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionFchInstall.h @@ -828,7 +828,7 @@ // // Define task list for InitReset phase // - FCH_TASK_ENTRY ROMDATA *FchInitResetTaskTable[] = { + FCH_TASK_ENTRY ROMDATA * CONST FchInitResetTaskTable[] = { InstallFchInitResetHwAcpiP, InstallFchInitResetAb, InstallFchInitResetSpi, diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionGnbInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionGnbInstall.h index f6fc162919..940ab9e472 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/OptionGnbInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionGnbInstall.h @@ -90,7 +90,7 @@ #if (GNB_TYPE_TN == TRUE) #include <Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h> #endif - GNB_SERVICE *ServiceTable = SERVICES_POINTER; + CONST GNB_SERVICE * CONST ServiceTable = SERVICES_POINTER; //--------------------------------------------------------------------------------------------------- // BUILD options @@ -254,7 +254,7 @@ #define CFG_LOADLINE_ENABLE TRUE #endif - GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = { + CONST GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = { CFG_IGFX_AS_PCIE_EP, CFG_LCLK_DEEP_SLEEP_EN, CFG_LCLK_DPM_EN, @@ -352,7 +352,7 @@ #endif //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = { + CONST OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = { OPTION_NBINITATEARLY_ENTRY OPTION_GNBEARLYINTERFACETN_ENTRY OPTION_F12NBSMUINITFEATURE_ENTRY @@ -384,7 +384,7 @@ #define OPTION_GNBEARLIERINTERFACETN_ENTRY #endif - OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[] = { + CONST OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[] = { OPTION_PCIECONFIGURATIONINIT_ENTRY OPTION_GNBEARLIERINTERFACETN_ENTRY {0, NULL} @@ -471,7 +471,7 @@ #endif //--------------------------------------------------------------------------------------------------- - OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = { + CONST OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = { OPTION_PCIEINITATPOSTEARLY_ENTRY OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY OPTION_GFXCONFIGPOSTINTERFACE_ENTRY @@ -480,7 +480,7 @@ {0, NULL} }; - OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = { + CONST OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = { OPTION_NBINITATPOST_ENTRY OPTION_GNBPOSTINTERFACETN_ENTRY OPTION_PCIEINITATPOST_ENTRY diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionMemoryInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionMemoryInstall.h index f662db285b..eaca53e129 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/OptionMemoryInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionMemoryInstall.h @@ -405,7 +405,7 @@ BOOLEAN MemFS3DefConstructorRet ( #define MEM_MAIN_FLOW_CONTROL_PTR_TN MemMFlowDef, #endif - MEM_FLOW_CFG* memFlowControlInstalled[] = { + MEM_FLOW_CFG* CONST memFlowControlInstalled[] = { MEM_MAIN_FLOW_CONTROL_PTR_Dr MEM_MAIN_FLOW_CONTROL_PTR_DA MEM_MAIN_FLOW_CONTROL_PTR_RB @@ -1209,7 +1209,7 @@ BOOLEAN MemFS3DefConstructorRet ( #define MEM_MAIN_FEATURE_TRAINING MemMStandardTraining #define MEM_FEATURE_TRAINING MemFStandardTraining - MEM_FEAT_BLOCK_NB MemFeatBlockTN = { + CONST MEM_FEAT_BLOCK_NB MemFeatBlockTN = { MEM_FEAT_BLOCK_NB_STRUCT_VERSION, MEM_FEATURE_ONLINE_SPARE, MEM_FEATURE_BANK_INTERLEAVE, @@ -1242,7 +1242,7 @@ BOOLEAN MemFS3DefConstructorRet ( * MAIN FEATURE BLOCK *--------------------------------------------------------------------------------------------------- */ - MEM_FEAT_BLOCK_MAIN MemFeatMain = { + CONST MEM_FEAT_BLOCK_MAIN MemFeatMain = { MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION, MEM_MAIN_FEATURE_TRAINING, MEM_MAIN_FEATURE_DIMM_EXCLUDE, @@ -2665,7 +2665,7 @@ BOOLEAN MemFS3DefConstructorRet ( #else #define TECH_TRAIN_MAX_RD_LAT_DDR3 MemTFeatDef #endif - MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3TN = { + CONST MEM_TECH_FEAT_BLOCK memTechTrainingFeatSequenceDDR3TN = { MEM_TECH_FEAT_BLOCK_STRUCT_VERSION, TECH_TRAIN_ENTER_HW_TRN_DDR3, TECH_TRAIN_SW_WL_DDR3, @@ -2725,7 +2725,7 @@ BOOLEAN MemFS3DefConstructorRet ( MEM_TECH_ENABLE_TRAINING_SEQUENCE_END }; - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { + CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DR MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_DA MEM_TECH_ENABLE_TRAINING_SEQUENCE_DDR3_HY @@ -2745,7 +2745,7 @@ BOOLEAN MemFS3DefConstructorRet ( * *--------------------------------------------------------------------------------------------------- */ - OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control + OPTION_MEM_FEATURE_NB* CONST memNTrainFlowControl[] = { // Training flow control NB_TRAIN_FLOW_DDR2, NB_TRAIN_FLOW_DDR3, }; @@ -2755,7 +2755,7 @@ BOOLEAN MemFS3DefConstructorRet ( * *--------------------------------------------------------------------------------------------------- */ - MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed + MEM_TECH_CONSTRUCTOR* CONST memTechInstalled[] = { // Types of technology installed MEM_TECH_CONSTRUCTOR_DDR2 MEM_TECH_CONSTRUCTOR_DDR3 NULL @@ -3665,7 +3665,7 @@ BOOLEAN MemFS3DefConstructorRet ( */ #define MEM_PSC_FLOW_BLOCK_END NULL #define PSC_TBL_END NULL - #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue + #define MEM_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, CONST MEM_PSC_TABLE_BLOCK *)) memDefTrue #if OPTION_MEMCTLR_OR #if OPTION_UDIMMS @@ -4517,43 +4517,43 @@ BOOLEAN MemFS3DefConstructorRet ( #define PSC_TBL_TN_CS_TRI_FP2 #endif - PSC_TBL_ENTRY* memPSCTblMaxFreqArrayTN[] = { + PSC_TBL_ENTRY* CONST memPSCTblMaxFreqArrayTN[] = { PSC_TBL_TN_SODIMM3_MAX_FREQ PSC_TBL_TN_SODWN_SODIMM3_MAX_FREQ PSC_TBL_TN_UDIMM3_MAX_FREQ PSC_TBL_END }; - PSC_TBL_ENTRY* memPSCTblDramTermArrayTN[] = { + PSC_TBL_ENTRY* CONST memPSCTblDramTermArrayTN[] = { PSC_TBL_TN_UDIMM3_DRAM_TERM PSC_TBL_TN_SODIMM3_DRAM_TERM PSC_TBL_TN_SODWN_SODIMM3_DRAM_TERM PSC_TBL_END }; - PSC_TBL_ENTRY* memPSCTblODTPatArrayTN[] = { + PSC_TBL_ENTRY* CONST memPSCTblODTPatArrayTN[] = { &TNOdtPatTblEnt, PSC_TBL_END }; - PSC_TBL_ENTRY* memPSCTblSAOArrayTN[] = { + PSC_TBL_ENTRY* CONST memPSCTblSAOArrayTN[] = { PSC_TBL_TN_SODIMM3_SAO PSC_TBL_TN_SODWN_SODIMM3_SAO PSC_TBL_TN_UDIMM3_SAO PSC_TBL_END }; - PSC_TBL_ENTRY* memPSCTblMR0WRArrayTN[] = { + PSC_TBL_ENTRY* CONST memPSCTblMR0WRArrayTN[] = { &TNMR0WrTblEntry, PSC_TBL_END }; - PSC_TBL_ENTRY* memPSCTblMR0CLArrayTN[] = { + PSC_TBL_ENTRY* CONST memPSCTblMR0CLArrayTN[] = { &TNMR0CLTblEntry, PSC_TBL_END }; - PSC_TBL_ENTRY* memPSCTblGenArrayTN[] = { + PSC_TBL_ENTRY* CONST memPSCTblGenArrayTN[] = { &TNDdr3CKETriEnt, PSC_TBL_TN_CLK_DIS_FM2 PSC_TBL_TN_ODT_TRI_FM2 @@ -4567,7 +4567,7 @@ BOOLEAN MemFS3DefConstructorRet ( PSC_TBL_END }; - PSC_TBL_ENTRY* memPSCTblS2DArrayTN[] = { + PSC_TBL_ENTRY* CONST memPSCTblS2DArrayTN[] = { PSC_TBL_TN_UDIMM3_S2D_FM2 PSC_TBL_TN_SODIMM3_S2D_FS1 PSC_TBL_TN_SODIMM3_S2D_FP2 @@ -4575,7 +4575,7 @@ BOOLEAN MemFS3DefConstructorRet ( PSC_TBL_END }; - MEM_PSC_TABLE_BLOCK memPSCTblBlockTN = { + CONST MEM_PSC_TABLE_BLOCK memPSCTblBlockTN = { (PSC_TBL_ENTRY **)&memPSCTblMaxFreqArrayTN, (PSC_TBL_ENTRY **)&memPSCTblDramTermArrayTN, (PSC_TBL_ENTRY **)&memPSCTblODTPatArrayTN, @@ -4599,7 +4599,7 @@ BOOLEAN MemFS3DefConstructorRet ( extern MEM_PSC_FLOW MemPGetSAO; extern MEM_PSC_FLOW MemPGetMR0WrCL; - MEM_PSC_FLOW_BLOCK memPlatSpecFlowTN = { + CONST MEM_PSC_FLOW_BLOCK memPlatSpecFlowTN = { &memPSCTblBlockTN, MemPGetMaxFreqSupported, MemPGetRttNomWr, @@ -4620,7 +4620,7 @@ BOOLEAN MemFS3DefConstructorRet ( #endif - MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { + CONST MEM_PSC_FLOW_BLOCK* CONST memPlatSpecFlowArray[] = { MEM_PSC_FLOW_BLOCK_OR MEM_PSC_FLOW_BLOCK_TN MEM_PSC_FLOW_BLOCK_END @@ -4641,7 +4641,7 @@ BOOLEAN MemFS3DefConstructorRet ( #else //#if (OPTION_LRDIMMS == FALSE) #define MEM_TECH_FEATURE_LRDIMM_INIT MemTFeatDef #endif - MEM_TECH_LRDIMM memLrdimmSupported = { + CONST MEM_TECH_LRDIMM memLrdimmSupported = { MEM_TECH_LRDIMM_STRUCT_VERSION, MEM_TECH_FEATURE_LRDIMM_INIT }; @@ -4652,7 +4652,7 @@ BOOLEAN MemFS3DefConstructorRet ( * *--------------------------------------------------------------------------------------------------- */ - MEM_FLOW_CFG* memFlowControlInstalled[] = { + MEM_FLOW_CFG* CONST memFlowControlInstalled[] = { NULL }; /*--------------------------------------------------------------------------------------------------- @@ -4661,7 +4661,7 @@ BOOLEAN MemFS3DefConstructorRet ( * *--------------------------------------------------------------------------------------------------- */ - OPTION_MEM_FEATURE_NB* memNTrainFlowControl[] = { // Training flow control + OPTION_MEM_FEATURE_NB* CONST memNTrainFlowControl[] = { // Training flow control NULL, NULL, }; @@ -4671,7 +4671,7 @@ BOOLEAN MemFS3DefConstructorRet ( * *--------------------------------------------------------------------------------------------------- */ - MEM_TECH_CONSTRUCTOR* memTechInstalled[] = { // Types of technology installed + MEM_TECH_CONSTRUCTOR* CONST memTechInstalled[] = { // Types of technology installed NULL }; @@ -4681,13 +4681,13 @@ BOOLEAN MemFS3DefConstructorRet ( * *--------------------------------------------------------------------------------------------------- */ - UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0}; + CONST UINT8 MemoryTechnologyMap[MAX_SOCKETS_SUPPORTED] = {0, 0, 0, 0, 0, 0, 0, 0}; /*--------------------------------------------------------------------------------------------------- * DEFAULT MAIN FEATURE BLOCK *--------------------------------------------------------------------------------------------------- */ - MEM_FEAT_BLOCK_MAIN MemFeatMain = { + CONST MEM_FEAT_BLOCK_MAIN MemFeatMain = { 0 }; @@ -4744,18 +4744,18 @@ BOOLEAN MemFS3DefConstructorRet ( *--------------------------------------------------------------------------------------------------- */ #if OPTION_DDR2 - MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = { + CONST MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR2 = { 0 }; - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { + CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR2[] = { { 0 } }; #endif #if OPTION_DDR3 - MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { + CONST MEM_TECH_FEAT_BLOCK memTechTrainingFeatDDR3 = { 0 }; - MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { + CONST MEM_FEAT_TRAIN_SEQ memTrainSequenceDDR3[] = { { 0 } }; #endif @@ -4766,52 +4766,52 @@ BOOLEAN MemFS3DefConstructorRet ( *--------------------------------------------------------------------------------------------------- */ #if (OPTION_MEMCTLR_DR == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDr[MAX_FF_TYPES] = { + MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledDr[MAX_FF_TYPES] = { NULL }; #endif #if (OPTION_MEMCTLR_RB == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledRb[MAX_FF_TYPES] = { + MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledRb[MAX_FF_TYPES] = { NULL }; #endif #if (OPTION_MEMCTLR_DA == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledDA[MAX_FF_TYPES] = { + MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledDA[MAX_FF_TYPES] = { NULL }; #endif #if (OPTION_MEMCTLR_Ni == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledNi[MAX_FF_TYPES] = { + MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledNi[MAX_FF_TYPES] = { NULL }; #endif #if (OPTION_MEMCTLR_PH == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledPh[MAX_FF_TYPES] = { + MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledPh[MAX_FF_TYPES] = { NULL }; #endif #if (OPTION_MEMCTLR_LN == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledLN[MAX_FF_TYPES] = { + MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledLN[MAX_FF_TYPES] = { NULL }; #endif #if (OPTION_MEMCTLR_HY == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledHy[MAX_FF_TYPES] = { + MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledHy[MAX_FF_TYPES] = { NULL }; #endif #if (OPTION_MEMCTLR_OR == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledOr[MAX_FF_TYPES] = { + MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledOr[MAX_FF_TYPES] = { NULL }; #endif #if (OPTION_MEMCTLR_C32 == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledC32[MAX_FF_TYPES] = { + MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledC32[MAX_FF_TYPES] = { NULL }; #endif #if (OPTION_MEMCTLR_ON == TRUE) - MEM_PLAT_SPEC_CFG* memPlatSpecFFInstalledON[MAX_FF_TYPES] = { + MEM_PLAT_SPEC_CFG* CONST memPlatSpecFFInstalledON[MAX_FF_TYPES] = { NULL }; #endif @@ -4820,7 +4820,7 @@ BOOLEAN MemFS3DefConstructorRet ( * *---------------------------------------------------------------------- */ - MEM_PLATFORM_CFG* memPlatformTypeInstalled[] = { + MEM_PLATFORM_CFG* CONST memPlatformTypeInstalled[] = { NULL }; @@ -4829,11 +4829,11 @@ BOOLEAN MemFS3DefConstructorRet ( * *---------------------------------------------------------------------- */ - MEM_PSC_FLOW_BLOCK* memPlatSpecFlowArray[] = { + MEM_PSC_FLOW_BLOCK* CONST memPlatSpecFlowArray[] = { NULL }; - MEM_TECH_LRDIMM memLrdimmSupported = { + CONST MEM_TECH_LRDIMM memLrdimmSupported = { MEM_TECH_LRDIMM_STRUCT_VERSION, NULL }; @@ -4845,7 +4845,7 @@ BOOLEAN MemFS3DefConstructorRet ( * *--------------------------------------------------------------------------------------------------- */ -MEM_NB_SUPPORT memNBInstalled[] = { +CONST MEM_NB_SUPPORT memNBInstalled[] = { MEM_NB_SUPPORT_RB MEM_NB_SUPPORT_DA MEM_NB_SUPPORT_Ni diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionMultiSocketInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionMultiSocketInstall.h index 46c303330b..2bf3eed648 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/OptionMultiSocketInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionMultiSocketInstall.h @@ -89,7 +89,7 @@ #endif /* Declare the instance of the multisocket option configuration structure */ -OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = { +CONST OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = { MULTISOCKET_STRUCT_VERSION, GET_NUM_PM_STEPS, CORE0_PM_TASK, diff --git a/src/vendorcode/amd/agesa/f15tn/Config/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/OptionPstateInstall.h index e80a69ddb3..8d5557b392 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/OptionPstateInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/OptionPstateInstall.h @@ -219,7 +219,7 @@ #endif /* Declare the instance of the PSTATE option configuration structure */ -OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = { +CONST OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = { PSTATE_STRUCT_VERSION, USER_PSTATE_OPTION_GATHER, USER_PSTATE_OPTION_LEVEL diff --git a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h index 798c1cc0cd..6071356dca 100644 --- a/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Config/PlatformInstall.h @@ -48,7 +48,7 @@ * ****************************************************************************/ -VOLATILE AMD_MODULE_HEADER mCpuModuleID = { +CONST AMD_MODULE_HEADER mCpuModuleID = { //ModuleHeaderSignature // Remove 'DOM$' as temp solution before update BinUtil.exe , Int32FromChar ('0', '0', '0', '0'), @@ -2624,7 +2624,7 @@ CONST UINT32 ROMDATA AmdPlatformTypeCgf = CFG_AMD_PLATFORM_TYPE; * ****************************************************************************/ -FCH_PLATFORM_POLICY FchUserOptions = { +CONST FCH_PLATFORM_POLICY FchUserOptions = { CFG_SMBUS0_BASE_ADDRESS, // CfgSmbus0BaseAddress CFG_SMBUS1_BASE_ADDRESS, // CfgSmbus1BaseAddress CFG_SIO_PME_BASE_ADDRESS, // CfgSioPmeBaseAddress @@ -2671,7 +2671,7 @@ FCH_PLATFORM_POLICY FchUserOptions = { CFG_FCH_GPIO_CONTROL_LIST // *CfgFchGpioControl }; -BUILD_OPT_CFG UserOptions = { +CONST BUILD_OPT_CFG UserOptions = { { // AGESA version string AGESA_CODE_SIGNATURE, // code header Signature AGESA_PACKAGE_STRING, // 8 character ID diff --git a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h index 2494ba98d9..41a416fbde 100644 --- a/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h +++ b/src/vendorcode/amd/agesa/f15tn/Include/OptionMemory.h @@ -123,7 +123,7 @@ typedef BOOLEAN OPTION_MEM_FEATURE_MAIN ( typedef BOOLEAN MEM_NB_CONSTRUCTOR ( IN OUT MEM_NB_BLOCK *NBPtr, IN OUT MEM_DATA_STRUCT *MemPtr, - IN MEM_FEAT_BLOCK_NB *FeatPtr, + CONST IN MEM_FEAT_BLOCK_NB *FeatPtr, IN MEM_SHARED_DATA *mmSharedPtr, ///< Pointer to Memory scratchpad IN UINT8 NodeID ); @@ -242,7 +242,7 @@ typedef struct _MEM_NB_SUPPORT { UINT16 MemNBSupportVersion; ///< Version of northbridge support. MEM_NB_CONSTRUCTOR *MemConstructNBBlock; ///< NorthBridge block constructor. MEM_INITIALIZER *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT. - MEM_FEAT_BLOCK_NB *MemFeatBlock; ///< Memory feature block. + CONST MEM_FEAT_BLOCK_NB *MemFeatBlock; ///< Memory feature block. MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor. MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification. } MEM_NB_SUPPORT; @@ -262,7 +262,7 @@ typedef struct _MEM_FEAT_TRAIN_SEQ { UINT16 OptMemTrainingSequenceListVersion; ///< Version of main feature block. OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function. OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function. - MEM_TECH_FEAT_BLOCK *MemTechFeatBlock; ///< Memory feature block. + CONST MEM_TECH_FEAT_BLOCK *MemTechFeatBlock; ///< Memory feature block. } MEM_FEAT_TRAIN_SEQ; /** @@ -289,7 +289,7 @@ typedef struct _MEM_PSC_TABLE_BLOCK { typedef BOOLEAN MEM_PSC_FLOW ( IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables + CONST IN MEM_PSC_TABLE_BLOCK *EntryOfTables ); /** @@ -297,7 +297,7 @@ typedef BOOLEAN MEM_PSC_FLOW ( * specific configuration. */ typedef struct _MEM_PSC_FLOW_BLOCK { - MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK + CONST MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK MEM_PSC_FLOW *MaxFrequency; ///< Sub-engine which performs "Max Frequency" value extraction. MEM_PSC_FLOW *DramTerm; ///< Sub-engine which performs "Dram Term" value extraction. MEM_PSC_FLOW *ODTPattern; ///< Sub-engine which performs "ODT Pattern" value extraction. diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.h index 126c4cf3e6..1b820ac98c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/S3.h @@ -260,23 +260,23 @@ typedef struct { typedef struct { UINT16 Version; ///< Version of header UINT16 NumRegisters; ///< Number of registers in the list - PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor - PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers + CONST PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor + CONST PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers } PCI_REGISTER_BLOCK_HEADER; /// S3 'conditional' PCI register list header. typedef struct { UINT16 Version; ///< Version of header UINT16 NumRegisters; ///< Number of registers in the list - CONDITIONAL_PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor - PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers + CONST CONDITIONAL_PCI_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor + CONST PCI_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers } CPCI_REGISTER_BLOCK_HEADER; /// S3 MSR register list header. typedef struct { UINT16 Version; ///< Version of header UINT16 NumRegisters; ///< Number of registers in the list - MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor + CONST MSR_REG_DESCRIPTOR *RegisterList; ///< Pointer to the first register descriptor MSR_SPECIAL_CASE *SpecialCases; ///< Pointer to array of special case handlers } MSR_REGISTER_BLOCK_HEADER; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c index 530931cebc..2bef0633fc 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/Table.c @@ -118,12 +118,12 @@ STATIC *GetNextRegisterTable ( IN CPU_SPECIFIC_SERVICES *FamilySpecificServices, IN TABLE_CORE_SELECTOR Selector, - IN OUT REGISTER_TABLE ***RegisterTableHandle, + CONST IN OUT REGISTER_TABLE ***RegisterTableHandle, OUT UINTN *NumberOfEntries, IN AMD_CONFIG_PARAMS *StdHeader ) { - REGISTER_TABLE **NextTable; + CONST REGISTER_TABLE **NextTable; TABLE_ENTRY_FIELDS *Entries; ASSERT ((FamilySpecificServices != NULL) && (StdHeader != NULL)); @@ -814,7 +814,7 @@ SetRegistersFromTables ( TABLE_ENTRY_FIELDS *Entries; TABLE_CORE_SELECTOR Selector; TABLE_ENTRY_TYPE EntryType; - REGISTER_TABLE **TableHandle; + CONST REGISTER_TABLE **TableHandle; UINTN NumberOfEntries; UINTN CurrentEntryCount; TABLE_ENTRY_TYPE_DESCRIPTOR *TypeImplementer; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h index f7d3b86220..603853abef 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/CPU/cpuFamilyTranslation.h @@ -851,7 +851,7 @@ struct _CPU_SPECIFIC_SERVICES { // See t PF_NEXT_LINK_HAS_HTFPY_FEATS NextLinkHasHtPhyFeats; ///< Method: Iterate over HT Links matching features, for HT PHY entries. PF_SET_HT_PHY_REGISTER SetHtPhyRegister; ///< Method: Set an Ht Phy register based on table entry. PF_GET_NEXT_HT_LINK_FEATURES GetNextHtLinkFeatures; ///< Method: Iterate over HT links, returning link features. - REGISTER_TABLE **RegisterTableList; ///< Public Data: The available register tables. + CONST REGISTER_TABLE **RegisterTableList; ///< Public Data: The available register tables. TABLE_ENTRY_TYPE_DESCRIPTOR *TableEntryTypeDescriptors; ///< Public Data: implemented register table entry types. PACKAGE_HTLINK_MAP PackageLinkMap; ///< Public Data: translate northbridge HT links to package level links, or NULL. CORE_PAIR_MAP *CorePairMap; ///< Public Data: translate compute unit core pairing, or NULL. @@ -1004,4 +1004,3 @@ GetEmptyArray ( ); #endif // _CPU_FAMILY_TRANSLATION_H_ - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c index 181b1fa2bf..a0a16baac7 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/AmdInitEarly.c @@ -74,7 +74,7 @@ RDATA_GROUP (G1_PEICC) * T Y P E D E F S A N D S T R U C T U R E S *---------------------------------------------------------------------------------------- */ -EXECUTION_CACHE_REGION InitExeCacheMap[] = +CONST EXECUTION_CACHE_REGION InitExeCacheMap[] = { {0x00000000, 0x00000000}, {0x00000000, 0x00000000}, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c index 94f5e12a27..d800dd75f0 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.c @@ -243,7 +243,7 @@ S3SaveStateSaveWriteOp ( IN ACCESS_WIDTH Width, IN UINT64 Address, IN UINT32 Count, - IN VOID *Buffer + CONST IN VOID *Buffer ) { S3_SAVE_TABLE_HEADER *S3SaveTablePtr; @@ -616,7 +616,7 @@ S3SaveDebugOpcodeString ( VOID S3SaveDebugPrintHexArray ( IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *Array, + CONST IN VOID *Array, IN UINT32 Count, IN ACCESS_WIDTH Width ) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.h b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.h index a2bdedb3e9..9b09d8701c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Common/S3SaveState.h @@ -192,7 +192,7 @@ S3ScriptGetS3SaveTable ( VOID S3SaveDebugPrintHexArray ( IN AMD_CONFIG_PARAMS *StdHeader, - IN VOID *Array, + CONST IN VOID *Array, IN UINT32 Count, IN ACCESS_WIDTH Width ); @@ -210,7 +210,7 @@ S3SaveStateSaveWriteOp ( IN ACCESS_WIDTH Width, IN UINT64 Address, IN UINT32 Count, - IN VOID *Buffer + CONST IN VOID *Buffer ); AGESA_STATUS diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h index 00283de4d9..7967b1dc4b 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchDef.h @@ -52,12 +52,12 @@ VOID ReadMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr); VOID WriteMem (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *ValuePtr); VOID RwMem (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data); VOID ReadPci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); -VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); +VOID WritePci (IN UINT32 Address, IN UINT8 OpFlag, CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); VOID RwPci (IN UINT32 Address, IN UINT8 OpFlag, IN UINT32 Mask, IN UINT32 Data, IN AMD_CONFIG_PARAMS *StdHeader); VOID ProgramPciByteTable (IN REG8_MASK* pPciByteTable, IN UINT16 dwTableSize, IN AMD_CONFIG_PARAMS *StdHeader); VOID ProgramFchAcpiMmioTbl (IN ACPI_REG_WRITE *pAcpiTbl, IN AMD_CONFIG_PARAMS *StdHeader); -VOID ProgramFchSciMapTbl (IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); -VOID ProgramFchGpioTbl (IN GPIO_CONTROL *pGpioTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); +VOID ProgramFchSciMapTbl (CONST IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); +VOID ProgramFchGpioTbl (CONST IN GPIO_CONTROL *pGpioTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); VOID ProgramFchSataPhyTbl (IN SATA_PHY_CONTROL *pSataPhyTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock); VOID GetChipSysMode (IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader); BOOLEAN IsImcEnabled (IN AMD_CONFIG_PARAMS *StdHeader); @@ -454,4 +454,3 @@ BOOLEAN IsLpcRom (OUT VOID); VOID SbSleepTrapControl (IN BOOLEAN SleepTrap); #endif - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c index 2960bde389..81a9cc32d8 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/FchPeLib.c @@ -137,7 +137,7 @@ ProgramFchAcpiMmioTbl ( */ VOID ProgramFchSciMapTbl ( - IN SCI_MAP_CONTROL *pSciMapTbl, + CONST IN SCI_MAP_CONTROL *pSciMapTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock ) { @@ -175,7 +175,7 @@ ProgramFchSciMapTbl ( */ VOID ProgramFchGpioTbl ( - IN GPIO_CONTROL *pGpioTbl, + CONST IN GPIO_CONTROL *pGpioTbl, IN FCH_RESET_DATA_BLOCK *FchResetDataBlock ) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c index 6d286e8e02..c479a5c6a1 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Common/PciLib.c @@ -63,7 +63,7 @@ VOID WritePci ( IN UINT32 Address, IN UINT8 OpFlag, - IN VOID *Value, + CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader ) { @@ -90,5 +90,3 @@ RwPci ( rMask = ~Mask; LibAmdPciRMW ((ACCESS_WIDTH) OpFlag, PciAddress, &Data, &rMask, StdHeader); } - - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c index 33adf862db..c5ad31ab61 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/HwAcpi/Family/Hudson2/Hudson2SSService.c @@ -55,7 +55,7 @@ * * */ -ACPI_REG_WRITE FchInitResetAcpiMmioTable[] = +CONST ACPI_REG_WRITE FchInitResetAcpiMmioTable[] = { {00, 00, 0xB0, 0xAC}, /// Signature {MISC_BASE >> 8, FCH_MISC_REG41, 0x1F, 0x40}, //keep Auxiliary_14Mclk_Sel [12] @@ -138,4 +138,3 @@ ProgramFchHwAcpiResetP ( LocalCfgPtr->SataClkMode = 0x0a; } } - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c index ba267c3b53..9f299a8ff4 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Interface/Family/Hudson2/ResetDefHudson2.c @@ -75,7 +75,7 @@ CONST FCH_RESET_INTERFACE ROMDATA FchResetInterfaceDefault = { * InitReset Phase Data Block Default (Failsafe) *---------------------------------------------------------------- */ -FCH_RESET_DATA_BLOCK InitResetCfgDefault = { +CONST FCH_RESET_DATA_BLOCK InitResetCfgDefault = { NULL, // StdHeader {0}, // FchReset @@ -154,5 +154,3 @@ FCH_RESET_DATA_BLOCK InitResetCfgDefault = { }, NULL // OemResetProgrammingTablePtr }; - - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c index bdb214df42..b78dd40214 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Pcib/PcibReset.c @@ -51,7 +51,7 @@ * * */ -REG8_MASK FchInitResetPcibPciTable[] = +CONST REG8_MASK FchInitResetPcibPciTable[] = { // // P2P Bridge (Bus 0, Dev 20, Func 4) @@ -98,7 +98,7 @@ FchInitResetPcib ( * * */ -REG8_MASK FchInitResetPcibPort80EnableTable[] = +CONST REG8_MASK FchInitResetPcibPort80EnableTable[] = { // // P2P Bridge (Bus 0, Dev 20, Func 4) @@ -133,4 +133,3 @@ FchInitResetPcibPort80Enable ( StdHeader ); } - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c index 107e181394..e5358663e3 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Fch/Spi/Family/Hudson2/Hudson2LpcResetService.c @@ -54,7 +54,7 @@ * * */ -REG8_MASK FchInitHudson2ResetLpcPciTable[] = +CONST REG8_MASK FchInitHudson2ResetLpcPciTable[] = { // // LPC Device (Bus 0, Dev 20, Func 3) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h index b93e164ac4..ea9e922089 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/Gnb.h @@ -148,8 +148,8 @@ typedef enum { typedef struct _GNB_SERVICE { GNB_SERVICE_ID ServiceId; ///< Service ID UINT64 Family; ///< CPU family - VOID *ServiceProtocol; ///< Service protocol - struct _GNB_SERVICE *NextService; ///< Pointer to next service + CONST VOID *ServiceProtocol; ///< Service protocol + CONST struct _GNB_SERVICE *NextService; ///< Pointer to next service } GNB_SERVICE; #define GNB_STRINGIZE(x) #x diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h index e8194f8202..357484ddbf 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Common/GnbPcie.h @@ -191,7 +191,7 @@ typedef struct { /// Table Register Entry typedef struct { - PCIE_PORT_REGISTER_ENTRY *Table; ///< Table + CONST PCIE_PORT_REGISTER_ENTRY *Table; ///< Table UINT32 Length; ///< Length } PCIE_PORT_REGISTER_TABLE_HEADER; @@ -204,7 +204,7 @@ typedef struct { /// Table Register Entry typedef struct { - PCIE_HOST_REGISTER_ENTRY *Table; ///< Table + CONST PCIE_HOST_REGISTER_ENTRY *Table; ///< Table UINT32 Length; ///< Length } PCIE_HOST_REGISTER_TABLE_HEADER; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c index 69137a0cbb..5ea3444cbb 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.c @@ -151,7 +151,7 @@ GnbLibPciIndirectWrite ( IN UINT32 Address, IN UINT32 IndirectAddress, IN ACCESS_WIDTH Width, - IN VOID *Value, + CONST IN VOID *Value, IN VOID *Config ) { @@ -501,11 +501,11 @@ AGESA_STATUS GnbLibLocateService ( IN GNB_SERVICE_ID ServiceId, IN UINT8 SocketId, - IN VOID **ServiceProtocol, + CONST IN VOID **ServiceProtocol, IN AMD_CONFIG_PARAMS *StdHeader ) { - GNB_SERVICE *SeviceEntry; + CONST GNB_SERVICE *SeviceEntry; CPU_LOGICAL_ID LogicalId; SeviceEntry = ServiceTable; GetLogicalIdOfSocket (SocketId, &LogicalId, StdHeader); @@ -518,4 +518,3 @@ GnbLibLocateService ( } return AGESA_UNSUPPORTED; } - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h index 04a1b5c464..6a98ee3184 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLib.h @@ -62,7 +62,7 @@ GnbLibPciIndirectWrite ( IN UINT32 Address, IN UINT32 IndirectAddress, IN ACCESS_WIDTH Width, - IN VOID *Value, + CONST IN VOID *Value, IN VOID *Config ); @@ -159,7 +159,7 @@ AGESA_STATUS GnbLibLocateService ( IN GNB_SERVICE_ID ServiceId, IN UINT8 SocketId, - IN VOID **ServiceProtocol, + CONST IN VOID **ServiceProtocol, IN AMD_CONFIG_PARAMS *StdHeader ); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c index e8467d3680..c99baee6a1 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.c @@ -86,7 +86,7 @@ VOID GnbLibPciWrite ( IN UINT32 Address, IN ACCESS_WIDTH Width, - IN VOID *Value, + CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader ) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h index 7fc88cf374..7915d97b4d 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbCommonLib/GnbLibPciAcc.h @@ -49,7 +49,7 @@ VOID GnbLibPciWrite ( IN UINT32 Address, IN ACCESS_WIDTH Width, - IN VOID *Value, + CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader ); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c index c9713f5852..356b7b1f76 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbPcieTranslation.c @@ -99,7 +99,7 @@ PcieFmConfigureEnginesLaneAllocation ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header); - Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (CONST VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieConfigService->PcieFmConfigureEnginesLaneAllocation (Wrapper, EngineType, ConfigurationId); @@ -135,7 +135,7 @@ PcieFmGetCoreConfigurationValue ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Wrapper->Header); - Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (CONST VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieInitService->PcieFmGetCoreConfigurationValue (Wrapper, CoreId, ConfigurationSignature, ConfigurationValue); @@ -170,7 +170,7 @@ PcieFmCheckPortPciDeviceMapping ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); - Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (CONST VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieConfigService->PcieFmCheckPortPciDeviceMapping (PortDescriptor, Engine); @@ -203,7 +203,7 @@ PcieFmDebugGetCoreConfigurationString ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); - Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (CONST VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieDebugService->PcieFmDebugGetCoreConfigurationString (Wrapper, ConfigurationValue); @@ -233,7 +233,7 @@ PcieFmDebugGetWrapperNameString ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Wrapper->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); - Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (CONST VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieDebugService->PcieFmDebugGetWrapperNameString (Wrapper); @@ -264,7 +264,7 @@ PcieFmDebugGetHostRegAddressSpaceString ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Silicon->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); - Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamDebugService, Complex->SocketId, (CONST VOID **)&PcieDebugService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieDebugService->PcieFmDebugGetHostRegAddressSpaceString (Silicon, AddressFrame); @@ -299,7 +299,7 @@ PcieFmCheckPortPcieLaneCanBeMuxed ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); - Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (CONST VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieConfigService->PcieFmCheckPortPcieLaneCanBeMuxed (PortDescriptor, Engine); @@ -330,7 +330,7 @@ PcieFmMapPortPciAddress ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); - Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamConfigService, Complex->SocketId, (CONST VOID **)&PcieConfigService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieConfigService->PcieFmMapPortPciAddress (Engine); @@ -358,7 +358,7 @@ PcieFmGetComplexDataLength ( { AGESA_STATUS Status; PCIe_FAM_CONFIG_SERVICES *PcieConfigService; - Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader); + Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (CONST VOID **)&PcieConfigService, StdHeader); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieConfigService->PcieFmGetComplexDataLength (SocketId, Length, StdHeader); @@ -388,7 +388,7 @@ PcieFmBuildComplexConfiguration ( { AGESA_STATUS Status; PCIe_FAM_CONFIG_SERVICES *PcieConfigService; - Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader); + Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (CONST VOID **)&PcieConfigService, StdHeader); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieConfigService->PcieFmBuildComplexConfiguration (SocketId, Buffer, StdHeader); @@ -419,7 +419,7 @@ PcieFmGetLinkSpeedCap ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); - Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (CONST VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieInitService->PcieFmGetLinkSpeedCap (Flags, Engine); @@ -449,7 +449,7 @@ PcieFmGetNativePhyLaneBitmap ( Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); Pcie = (PCIe_PLATFORM_CONFIG *) PcieConfigGetParent (DESCRIPTOR_PLATFORM, &Complex->Header); - Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (CONST VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieInitService->PcieFmGetNativePhyLaneBitmap (PhyLaneBitmap, Engine); @@ -479,7 +479,7 @@ PcieFmSetLinkSpeedCap ( PCIe_FAM_INIT_SERVICES *PcieInitService; Complex = (PCIe_COMPLEX_CONFIG *) PcieConfigGetParent (DESCRIPTOR_COMPLEX, &Engine->Header); - Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); + Status = GnbLibLocateService (GnbPcieFamInitService, Complex->SocketId, (CONST VOID **)&PcieInitService, GnbLibGetHeader (Pcie)); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { PcieInitService->PcieFmSetLinkSpeedCap (LinkSpeedCapability, Engine, Pcie); @@ -505,11 +505,10 @@ PcieFmGetSbConfigInfo ( { AGESA_STATUS Status; PCIe_FAM_CONFIG_SERVICES *PcieConfigService; - Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (VOID **)&PcieConfigService, StdHeader); + Status = GnbLibLocateService (GnbPcieFamConfigService, SocketId, (CONST VOID **)&PcieConfigService, StdHeader); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return PcieConfigService->PcieFmGetSbConfigInfo (SocketId, SbPort, StdHeader); } return Status; } - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c index 8097e6413e..79de6df3fa 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbFamTranslation/GnbTranslation.c @@ -91,7 +91,7 @@ GnbFmCheckIommuPresent ( { AGESA_STATUS Status; GNB_FAM_IOMMU_SERVICES *GnbIommuConfigService; - Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (VOID **)&GnbIommuConfigService, StdHeader); + Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GnbIommuConfigService, StdHeader); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return GnbIommuConfigService->GnbFmCheckIommuPresent (GnbHandle, StdHeader); @@ -121,7 +121,7 @@ GnbFmCreateIvrsEntry ( { AGESA_STATUS Status; GNB_FAM_IOMMU_SERVICES *GnbIommuConfigService; - Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (VOID **)&GnbIommuConfigService, StdHeader); + Status = GnbLibLocateService (GnbIommuService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GnbIommuConfigService, StdHeader); ASSERT (Status == AGESA_SUCCESS); if (Status == AGESA_SUCCESS) { return GnbIommuConfigService->GnbFmCreateIvrsEntry (GnbHandle, Type, Ivrs, StdHeader); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h index 93381e3608..bb029a348f 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbCacWeightsTN.h @@ -45,7 +45,7 @@ #ifndef _GNBCACWEIGHTSTABLETN_H_ #define _GNBCACWEIGHTSTABLETN_H_ -UINT32 CacWeightsTN[] = { +CONST UINT32 CacWeightsTN[] = { 0xD65, 0x289A, 0x289A, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h index 1be9d7cafc..dc7cb1556c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbInitTNInstall.h @@ -66,7 +66,7 @@ extern F_PCIEFMMAPPORTPCIADDRESS PcieMapPortPciAddressTN; extern F_PCIEFMCHECKPORTPCIELANECANBEMUXED PcieCheckPortPcieLaneCanBeMuxedTN; extern F_PCIEFMGETSBCONFIGINFO PcieGetSbConfigInfoTN; - PCIe_FAM_CONFIG_SERVICES GnbPcieConfigProtocolTN = { +CONST PCIe_FAM_CONFIG_SERVICES GnbPcieConfigProtocolTN = { PcieGetComplexDataLengthTN, PcieBuildComplexConfigurationTN, PcieConfigureEnginesLaneAllocationTN, @@ -76,7 +76,7 @@ PcieGetSbConfigInfoTN }; - GNB_SERVICE GnbPcieCongigServicesTN = { + CONST GNB_SERVICE GnbPcieCongigServicesTN = { GnbPcieFamConfigService, AMD_FAMILY_TN, &GnbPcieConfigProtocolTN, @@ -92,14 +92,14 @@ extern F_PCIEFMGETNATIVEPHYLANEBITMAP PcieGetNativePhyLaneBitmapTN; extern F_PCIEFMSETLINKSPEEDCAP PcieSetLinkSpeedCapV4; - PCIe_FAM_INIT_SERVICES GnbPcieInitProtocolTN = { + CONST PCIe_FAM_INIT_SERVICES GnbPcieInitProtocolTN = { PcieGetCoreConfigurationValueTN, PcieGetLinkSpeedCapTN, PcieGetNativePhyLaneBitmapTN, PcieSetLinkSpeedCapV4 }; - GNB_SERVICE GnbPcieInitServicesTN = { + CONST GNB_SERVICE GnbPcieInitServicesTN = { GnbPcieFamInitService, AMD_FAMILY_TN, &GnbPcieInitProtocolTN, @@ -116,13 +116,13 @@ extern F_PCIEFMDEBUGGETWRAPPERNAMESTRING PcieDebugGetWrapperNameStringTN; extern F_PCIEFMDEBUGGETCORECONFIGURATIONSTRING PcieDebugGetCoreConfigurationStringTN; - PCIe_FAM_DEBUG_SERVICES GnbPcieDebugProtocolTN = { + CONST PCIe_FAM_DEBUG_SERVICES GnbPcieDebugProtocolTN = { PcieDebugGetHostRegAddressSpaceStringTN, PcieDebugGetWrapperNameStringTN, PcieDebugGetCoreConfigurationStringTN }; - GNB_SERVICE GnbPcieDebugServicesTN = { + CONST GNB_SERVICE GnbPcieDebugServicesTN = { GnbPcieFamDebugService, AMD_FAMILY_TN, &GnbPcieDebugProtocolTN, @@ -138,12 +138,12 @@ extern F_GNB_REGISTER_ACCESS GnbRegisterReadServiceTN; extern F_GNB_REGISTER_ACCESS GnbRegisterWriteServiceTN; - GNB_REGISTER_SERVICE GnbRegiterAccessProtocol = { + CONST GNB_REGISTER_SERVICE GnbRegiterAccessProtocol = { GnbRegisterReadServiceTN, GnbRegisterWriteServiceTN }; - GNB_SERVICE GnbRegisterAccessServicesTN = { + CONST GNB_SERVICE GnbRegisterAccessServicesTN = { GnbRegisterAccessService, AMD_FAMILY_TN, &GnbRegiterAccessProtocol, @@ -155,12 +155,12 @@ extern F_GNBFMCREATEIVRSENTRY GnbCreateIvrsEntryTN; extern F_GNBFMCHECKIOMMUPRESENT GnbCheckIommuPresentTN; - GNB_FAM_IOMMU_SERVICES GnbIommuConfigProtocolTN = { + CONST GNB_FAM_IOMMU_SERVICES GnbIommuConfigProtocolTN = { GnbCheckIommuPresentTN, GnbCreateIvrsEntryTN }; - GNB_SERVICE GnbIommuConfigServicesTN = { + CONST GNB_SERVICE GnbIommuConfigServicesTN = { GnbIommuService, AMD_FAMILY_TN, &GnbIommuConfigProtocolTN, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c index f8e885cc48..fa6dafd48c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.c @@ -242,7 +242,7 @@ GnbDctAdditionalDataWriteTN ( IN UINT8 DctCfgSel, IN UINT8 MemPsSel, IN UINT32 Flags, - IN VOID *Value, + CONST IN VOID *Value, IN AMD_CONFIG_PARAMS *StdHeader ) { @@ -816,7 +816,7 @@ AGESA_STATUS GnbRegisterWriteTN ( IN UINT8 RegisterSpaceType, IN UINT32 Address, - IN VOID *Value, + CONST IN VOID *Value, IN UINT32 Flags, IN AMD_CONFIG_PARAMS *StdHeader ) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h index d28c614292..3d5497ea09 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbRegisterAccTN.h @@ -49,7 +49,7 @@ AGESA_STATUS GnbRegisterWriteTN ( IN UINT8 RegisterSpaceType, IN UINT32 Address, - IN VOID *Value, + CONST IN VOID *Value, IN UINT32 Flags, IN AMD_CONFIG_PARAMS *StdHeader ); diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h index 1ce5fa2bc9..39581d6a7b 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbSmuFirmwareTN.h @@ -45,7 +45,7 @@ #ifndef _GNBSMUFIRMWARETN_H_ #define _GNBSMUFIRMWARETN_H_ -UINT32 FirmwareTNHeader [] = { +CONST UINT32 FirmwareTNHeader [] = { 0x554D535F, 0x554D535F, 0x0000F030, @@ -60,7 +60,7 @@ UINT32 FirmwareTNHeader [] = { 0x00000000, }; -UINT32 FirmwareTN[] = { +CONST UINT32 FirmwareTN[] = { 0x000a000e, 0x00000040, 0x00003bc0, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c index 6b855ae984..8196b79f8a 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/GnbTablesTN.c @@ -82,7 +82,7 @@ * P R O T O T Y P E S O F L O C A L F U N C T I O N S *---------------------------------------------------------------------------------------- */ -GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuTN [] = { +CONST GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuTN [] = { GNB_ENTRY_RMW ( D0F0x98_x07_TYPE, D0F0x98_x07_ADDRESS, @@ -99,7 +99,7 @@ GNB_TABLE ROMDATA GnbEarlierInitTableBeforeSmuTN [] = { GNB_ENTRY_TERMINATE }; -GNB_TABLE ROMDATA GnbEarlierInitTableAfterSmuTN [] = { +CONST GNB_TABLE ROMDATA GnbEarlierInitTableAfterSmuTN [] = { // Config GFX to legacy mode initially GNB_ENTRY_RMW ( D0F0x64_x1D_TYPE, @@ -284,7 +284,7 @@ GNB_TABLE ROMDATA GnbEarlierInitTableAfterSmuTN [] = { GNB_ENTRY_TERMINATE }; -GNB_TABLE ROMDATA GnbEarlyInitTableTN [] = { +CONST GNB_TABLE ROMDATA GnbEarlyInitTableTN [] = { GNB_ENTRY_WR ( D0F0x04_TYPE, D0F0x04_ADDRESS, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c index 60ea236c61..705afda46e 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieComplexDataTN.c @@ -73,7 +73,7 @@ */ -TN_COMPLEX_CONFIG ComplexDataTN = { +CONST TN_COMPLEX_CONFIG ComplexDataTN = { //Silicon { { @@ -461,4 +461,3 @@ TN_COMPLEX_CONFIG ComplexDataTN = { {0, 0, 0, 0, 0, 0} } }; - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c index da962d52e3..3f81825311 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieConfigTN.c @@ -946,7 +946,7 @@ PcieGetNativePhyLaneBitmapTN ( return PhyLaneBitmap; } -STATIC PCIe_PORT_DESCRIPTOR DefaultSbPortTN = { +STATIC CONST PCIe_PORT_DESCRIPTOR DefaultSbPortTN = { 0, PCIE_ENGINE_DATA_INITIALIZER (PciePortEngine, 0, 3), PCIE_PORT_DATA_INITIALIZER (PortEnabled, ChannelTypeLowLoss, 8, HotplugDisabled, PcieGenMaxSupported, PcieGenMaxSupported, AspmL0sL1, 0) @@ -972,4 +972,3 @@ PcieGetSbConfigInfoTN ( LibAmdMemCopy (SbPort, &DefaultSbPortTN, sizeof (DefaultSbPortTN), StdHeader); return AGESA_SUCCESS; } - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c index a58e918a22..832faba250 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbInitTN/PcieTablesTN.c @@ -75,7 +75,7 @@ *---------------------------------------------------------------------------------------- */ -STATIC PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = { +STATIC CONST PCIE_HOST_REGISTER_ENTRY PcieInitEarlyTable ROMDATA[] = { { WRAP_SPACE (GPP_WRAP_ID, D0F0xE4_WRAP_8016_ADDRESS), D0F0xE4_WRAP_8016_CalibAckLatency_MASK, @@ -113,7 +113,7 @@ CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA PcieInitEarlyTableTN = { ARRAY_SIZE(PcieInitEarlyTable) }; -STATIC PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = { +STATIC CONST PCIE_HOST_REGISTER_ENTRY ROMDATA CoreInitTable [] = { { D0F0xE4_CORE_0020_ADDRESS, D0F0xE4_CORE_0020_CiRcOrderingDis_MASK | @@ -164,7 +164,7 @@ CONST PCIE_HOST_REGISTER_TABLE_HEADER ROMDATA CoreInitTableTN = { }; -STATIC PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = { +STATIC CONST PCIE_PORT_REGISTER_ENTRY ROMDATA PortInitEarlyTable [] = { { DxF0xE4_x02_ADDRESS, DxF0xE4_x02_RegsLcAllowTxL1Control_MASK, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c index ddcbccbe55..1a09d58f35 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieTopologyServices.c @@ -154,7 +154,7 @@ PcieTopologyPrepareForReconfig ( } -UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; +CONST UINT8 LaneMuxSelectorTable[8] = { 0, 1, 2, 3, 4, 5, 6, 7 }; /*----------------------------------------------------------------------------------------*/ /** diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c index 4e3f2847c1..fde8852559 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.c @@ -148,7 +148,7 @@ BOOLEAN PcieUtilSearchArray ( IN UINT8 *Buf1, IN UINTN Buf1Length, - IN UINT8 *Buf2, + CONST IN UINT8 *Buf2, IN UINTN Buf2Length ) { @@ -156,7 +156,7 @@ PcieUtilSearchArray ( CurrentBuf1Ptr = Buf1; while (CurrentBuf1Ptr < (Buf1 + Buf1Length - Buf2Length)) { UINT8 *SourceBufPtr; - UINT8 *PatternBufPtr; + CONST UINT8 *PatternBufPtr; UINTN PatternBufLength; SourceBufPtr = CurrentBuf1Ptr; PatternBufPtr = Buf2; @@ -522,7 +522,7 @@ PcieUtilGetWrapperLaneBitMap ( VOID PciePortProgramRegisterTable ( - IN PCIE_PORT_REGISTER_ENTRY *Table, + CONST IN PCIE_PORT_REGISTER_ENTRY *Table, IN UINTN Length, IN PCIe_ENGINE_CONFIG *Engine, IN BOOLEAN S3Save, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h index 5ed4fc46cc..e9669e87d0 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieInitLibV1/PcieUtilityLib.h @@ -65,7 +65,7 @@ BOOLEAN PcieUtilSearchArray ( IN UINT8 *Buf1, IN UINTN Buf1Length, - IN UINT8 *Buf2, + CONST IN UINT8 *Buf2, IN UINTN Buf2Length ); @@ -109,7 +109,7 @@ PcieUtilGetWrapperLaneBitMap ( VOID PciePortProgramRegisterTable ( - IN PCIE_PORT_REGISTER_ENTRY *Table, + CONST IN PCIE_PORT_REGISTER_ENTRY *Table, IN UINTN Length, IN PCIe_ENGINE_CONFIG *Engine, IN BOOLEAN S3Save, diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c index f8a35cc58d..a40dbade52 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbPcieTrainingV1/PcieTraining.c @@ -354,9 +354,9 @@ PcieTrainingDetectPresence ( } } -UINT8 FailPattern1 [] = {0x2a, 0x6}; -UINT8 FailPattern2 [] = {0x2a, 0x9}; -UINT8 FailPattern3 [] = {0x2a, 0xb}; +CONST UINT8 FailPattern1 [] = {0x2a, 0x6}; +CONST UINT8 FailPattern2 [] = {0x2a, 0x9}; +CONST UINT8 FailPattern3 [] = {0x2a, 0xb}; /*----------------------------------------------------------------------------------------*/ /** diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c index f8faa3633f..ea572b981c 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/GNB/Modules/GnbTable/GnbTable.c @@ -125,7 +125,7 @@ GnbProcessTable ( WriteAccFlags |= GNB_REG_ACC_FLAG_S3SAVE; } - Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (VOID **)&GnbRegisterAccessProtocol, StdHeader); + Status = GnbLibLocateService (GnbRegisterAccessService, GnbGetSocketId (GnbHandle), (CONST VOID **)&GnbRegisterAccessProtocol, StdHeader); ASSERT (Status == AGESA_SUCCESS); while (*EntryPointer != GnbEntryTerminate) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c index 2449ff9c07..be184c9a4b 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Feat/S3/mfs3.c @@ -384,7 +384,7 @@ MemFS3GetPciDeviceRegisterList ( { AGESA_STATUS RetVal; S3_MEM_NB_BLOCK *S3NBPtr; - VOID *RegisterHeader; + CONST VOID *RegisterHeader; LOCATE_HEAP_PTR LocHeap; AGESA_BUFFER_PARAMS LocBufferParams; LocHeap.BufferHandle = AMD_MEM_S3_NB_HANDLE; @@ -434,7 +434,7 @@ MemFS3GetCPciDeviceRegisterList ( { AGESA_STATUS RetVal; S3_MEM_NB_BLOCK *S3NBPtr; - VOID *RegisterHeader; + CONST VOID *RegisterHeader; LOCATE_HEAP_PTR LocHeap; AGESA_BUFFER_PARAMS LocBufferParams; @@ -484,7 +484,7 @@ MemFS3GetMsrDeviceRegisterList ( { AGESA_STATUS RetVal; S3_MEM_NB_BLOCK *S3NBPtr; - VOID *RegisterHeader; + CONST VOID *RegisterHeader; LOCATE_HEAP_PTR LocHeap; AGESA_BUFFER_PARAMS LocBufferParams; @@ -534,7 +534,7 @@ MemFS3GetCMsrDeviceRegisterList ( { AGESA_STATUS RetVal; S3_MEM_NB_BLOCK *S3NBPtr; - VOID *RegisterHeader; + CONST VOID *RegisterHeader; LOCATE_HEAP_PTR LocHeap; AGESA_BUFFER_PARAMS LocBufferParams; diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c index 346489220e..b306933824 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Main/mmMemRestore.c @@ -84,7 +84,7 @@ BOOLEAN STATIC MemMSetCSRNb ( IN OUT MEM_NB_BLOCK *NBPtr, - IN PCI_SPECIAL_CASE *SpecialCases, + CONST IN PCI_SPECIAL_CASE *SpecialCases, IN PCI_ADDR PciAddr, IN UINT32 Value ); @@ -532,7 +532,7 @@ BOOLEAN STATIC MemMSetCSRNb ( IN OUT MEM_NB_BLOCK *NBPtr, - IN PCI_SPECIAL_CASE *SpecialCases, + CONST IN PCI_SPECIAL_CASE *SpecialCases, IN PCI_ADDR PciAddr, IN UINT32 Value ) diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c index c14ab4a8cc..8fe87d0280 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/NB/TN/mns3tn.c @@ -96,7 +96,7 @@ AGESA_STATUS STATIC MemNS3GetDeviceRegLstTN ( IN UINT32 RegisterLstID, - OUT VOID **RegisterHeader + CONST OUT VOID **RegisterHeader ); VOID @@ -189,7 +189,7 @@ MemS3ResumeConstructNBBlockTN ( * *---------------------------------------------------------------------------- */ -PCI_SPECIAL_CASE PciSpecialCaseFuncTN[] = { +CONST PCI_SPECIAL_CASE PciSpecialCaseFuncTN[] = { {MemNS3GetCSRTN, MemNS3SetCSRTN}, {MemNS3GetBitFieldNb, MemNS3SetBitFieldNb}, {MemNS3GetNBPStateDepRegUnb, MemNS3SetNBPStateDepRegUnb}, @@ -207,7 +207,7 @@ PCI_SPECIAL_CASE PciSpecialCaseFuncTN[] = { { (VOID (*) (ACCESS_WIDTH, PCI_ADDR, VOID *, VOID *)) memDefRet, MemNS3ForceNBP0Unb} }; -PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorTN[] = { +CONST PCI_REG_DESCRIPTOR ROMDATA S3PciPreSelfRefDescriptorTN[] = { {{14,3, 1}, DO_NOT_CARE, 0, 0}, {{0, 0, 0}, FUNC_2, 0x110, 0xFFFFF8E7}, {{0, 0, 0}, FUNC_1, 0x40, 0xFFFF0703}, @@ -233,7 +233,7 @@ CONST PCI_REGISTER_BLOCK_HEADER ROMDATA S3PciPreSelfRefTN = { PciSpecialCaseFuncTN }; -CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorTN[] = { +CONST CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPreSelfDescriptorTN[] = { // DCT 0 {{7, 0, 1}, DCT0, 0x40, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, {{7, 0, 1}, DCT0, 0x44, 0x7FF8FFED, DCT0_MASK, DCT0_ANY_DIMM_MASK}, @@ -515,7 +515,7 @@ CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPreSelfRefTN = { PciSpecialCaseFuncTN }; -CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorTN[] = { +CONST CONDITIONAL_PCI_REG_DESCRIPTOR ROMDATA S3CPciPostSelfDescriptorTN[] = { // DCT0 {{12, 2, 1}, DCT1, BFChAM1FenceSave, 0, DCT0_MEMPSTATE_MASK, ANY_DIMM_MASK}, {{1, 2, 1}, DCT0, BFRx4thStgEn, 0, DCT0_MASK, ANY_DIMM_MASK}, @@ -802,7 +802,7 @@ CONST CPCI_REGISTER_BLOCK_HEADER ROMDATA S3CPciPostSelfRefTN = { PciSpecialCaseFuncTN }; -MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorTN[] = { +CONST MSR_REG_DESCRIPTOR ROMDATA S3MSRPreSelfRefDescriptorTN[] = { {{0, 0, 0}, 0xC0010010, 0x00000000007F0000}, {{0, 0, 0}, 0xC001001A, 0x0000FFFFFF800000}, {{0, 0, 0}, 0xC001001D, 0x0000FFFFFF800000}, @@ -816,7 +816,7 @@ CONST MSR_REGISTER_BLOCK_HEADER ROMDATA S3MSRPreSelfRefTN = { NULL }; -VOID *MemS3RegListTN[] = { +CONST VOID * CONST MemS3RegListTN[] = { (VOID *)&S3PciPreSelfRefTN, NULL, (VOID *)&S3CPciPreSelfRefTN, @@ -992,7 +992,7 @@ AGESA_STATUS STATIC MemNS3GetDeviceRegLstTN ( IN UINT32 RegisterLstID, - OUT VOID **RegisterHeader + CONST OUT VOID **RegisterHeader ) { if (RegisterLstID >= (sizeof (MemS3RegListTN) / sizeof (VOID *))) { diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c index 2f6ef5db61..d195ce3b6b 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Ps/mp.c @@ -93,7 +93,7 @@ BOOLEAN STATIC MemPPSCGen ( IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables + CONST IN MEM_PSC_TABLE_BLOCK *EntryOfTables ); BOOLEAN @@ -551,7 +551,7 @@ BOOLEAN STATIC MemPPSCGen ( IN OUT MEM_NB_BLOCK *NBPtr, - IN MEM_PSC_TABLE_BLOCK *EntryOfTables + CONST IN MEM_PSC_TABLE_BLOCK *EntryOfTables ) { UINT8 i; @@ -1216,4 +1216,3 @@ MemPCheckTblDrvOverrideConfigSpeedLimit ( return FALSE; } - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c index 46e591aa5a..1706b7ef36 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/Tech/mttEdgeDetect.c @@ -101,7 +101,7 @@ RDATA_GROUP (G1_PEICC) * Sweep Table For Byte Training without insertion delay * */ -DQS_POS_SWEEP_TABLE SweepTableByte[] = +CONST DQS_POS_SWEEP_TABLE SweepTableByte[] = { // Begin End Inc/Dec Step EndResult Edge { 0x00, 0x1F, INC_DELAY, 4, 0xFFFF, LEFT_EDGE}, /// For Left Edge, start from 0 and Increment to 0x1F by 4 until all PASS @@ -113,7 +113,7 @@ DQS_POS_SWEEP_TABLE SweepTableByte[] = * Sweep Table For Byte Training with insertion delay * */ -DQS_POS_SWEEP_TABLE InsSweepTableByte[] = +CONST DQS_POS_SWEEP_TABLE InsSweepTableByte[] = { // Begin End Inc/Dec Step EndResult Edge { 0x00, -0x20, DEC_DELAY, -4, 0xFE00, LEFT_EDGE}, /// For Left Edge, start from 0 and Decrement to -0x20 by -4 until all FAIL @@ -400,7 +400,7 @@ MemTTrainDQSEdgeDetect ( { MEM_NB_BLOCK *NBPtr; DIE_STRUCT *MCTPtr; - DQS_POS_SWEEP_TABLE *SweepTablePtr; + CONST DQS_POS_SWEEP_TABLE *SweepTablePtr; UINT8 SweepTableSize; SWEEP_INFO SweepData; BOOLEAN Status; @@ -903,4 +903,3 @@ MemTDataEyeSave ( return TRUE; } - diff --git a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h index 657c8dfe41..08a07568fb 100644 --- a/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h +++ b/src/vendorcode/amd/agesa/f15tn/Proc/Mem/mfs3.h @@ -98,7 +98,7 @@ typedef struct _S3_MEM_NB_BLOCK { UINT16 (*MemS3GetRegLstPtr) (MEM_NB_BLOCK *NBPtr, DESCRIPTOR_GROUP *DescriptPtr); ///< Get register list pointer for both PCI and MSR register BOOLEAN (*MemS3Resume) (struct _S3_MEM_NB_BLOCK *S3NBPtr, UINT8 NodeID);///< Exit Self Refresh VOID (*MemS3RestoreScrub) (MEM_NB_BLOCK *NBPtr, UINT8 NodeID);///< Restore scrubber base - AGESA_STATUS (*MemS3GetDeviceRegLst) (UINT32 ReigsterLstID, VOID **RegisterHeader); ///< Get register list for a device + AGESA_STATUS (*MemS3GetDeviceRegLst) (UINT32 ReigsterLstID, CONST VOID **RegisterHeader); ///< Get register list for a device } S3_MEM_NB_BLOCK; /// Header for heap space to store the special case register. diff --git a/src/vendorcode/amd/agesa/f16kb/Config/OptionPstateInstall.h b/src/vendorcode/amd/agesa/f16kb/Config/OptionPstateInstall.h index a3c5fa3328..06b14bcb66 100644 --- a/src/vendorcode/amd/agesa/f16kb/Config/OptionPstateInstall.h +++ b/src/vendorcode/amd/agesa/f16kb/Config/OptionPstateInstall.h @@ -196,13 +196,13 @@ #endif /* Declare the instance of the PSTATE option configuration structure */ -OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = { +CONST OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = { PSTATE_STRUCT_VERSION, USER_PSTATE_OPTION_GATHER, USER_PSTATE_OPTION_LEVEL }; -OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = { +CONST OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = { PSTATE_STRUCT_VERSION, USER_SSDT_MAIN, USER_PSTATE_OPTION_MAIN, |