diff options
| -rw-r--r-- | src/soc/intel/meteorlake/chip.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/include/soc/pcie.h | 1 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/pcie_rp.c | 16 |
3 files changed, 20 insertions, 0 deletions
diff --git a/src/soc/intel/meteorlake/chip.c b/src/soc/intel/meteorlake/chip.c index 03adfdb738..51e89dcf3a 100644 --- a/src/soc/intel/meteorlake/chip.c +++ b/src/soc/intel/meteorlake/chip.c @@ -185,6 +185,9 @@ void soc_init_pre_device(void *chip_info) /* Swap enabled PCI ports in device tree if needed. */ pcie_rp_update_devicetree(get_pcie_rp_table()); + /* Swap enabled TBT root ports in device tree if needed. */ + pcie_rp_update_devicetree(get_tbt_pcie_rp_table()); + /* * Earlier when coreboot used to send EOP at late as possible caused * issue of delayed response from CSE since CSE was busy loading payload. diff --git a/src/soc/intel/meteorlake/include/soc/pcie.h b/src/soc/intel/meteorlake/include/soc/pcie.h index f97543c916..7c098e9ca5 100644 --- a/src/soc/intel/meteorlake/include/soc/pcie.h +++ b/src/soc/intel/meteorlake/include/soc/pcie.h @@ -6,5 +6,6 @@ #include <intelblocks/pcie_rp.h> const struct pcie_rp_group *get_pcie_rp_table(void); +const struct pcie_rp_group *get_tbt_pcie_rp_table(void); #endif /* __SOC_METEORLAKE_PCIE_H__ */ diff --git a/src/soc/intel/meteorlake/pcie_rp.c b/src/soc/intel/meteorlake/pcie_rp.c index 9f59ce1f97..7cfe3ed291 100644 --- a/src/soc/intel/meteorlake/pcie_rp.c +++ b/src/soc/intel/meteorlake/pcie_rp.c @@ -5,6 +5,17 @@ #include <soc/pcie.h> #include <soc/soc_info.h> +/* + * TBT's LCAP registers are returning port index which starts from 0x10 (Usually for other PCIe + * root ports index starts from 1). Thus keeping lcap_port_base 0x10 for TBT, so that coreboot's + * PCIe remapping logic can return correct index (0-based) + */ + +static const struct pcie_rp_group tbt_rp_groups[] = { + { .slot = PCI_DEV_SLOT_TBT, .count = CONFIG_MAX_TBT_ROOT_PORTS, .lcap_port_base = 0x10 }, + { 0 } +}; + static const struct pcie_rp_group mtlp_rp_groups[] = { { .slot = PCI_DEV_SLOT_PCIE_1, .start = 0, .count = 8, .lcap_port_base = 1 }, { .slot = PCI_DEV_SLOT_PCIE_2, .start = 0, .count = 3, .lcap_port_base = 1 }, @@ -17,6 +28,11 @@ const struct pcie_rp_group *get_pcie_rp_table(void) return mtlp_rp_groups; } +const struct pcie_rp_group *get_tbt_pcie_rp_table(void) +{ + return tbt_rp_groups; +} + enum pcie_rp_type soc_get_pcie_rp_type(const struct device *dev) { return PCIE_RP_PCH; |