diff options
| -rw-r--r-- | src/soc/intel/cannonlake/elog.c | 82 |
1 files changed, 81 insertions, 1 deletions
diff --git a/src/soc/intel/cannonlake/elog.c b/src/soc/intel/cannonlake/elog.c index 0bccdb7880..a2c359fe10 100644 --- a/src/soc/intel/cannonlake/elog.c +++ b/src/soc/intel/cannonlake/elog.c @@ -17,6 +17,7 @@ #include <bootstate.h> #include <cbmem.h> #include <console/console.h> +#include <device/pci_ops.h> #include <stdint.h> #include <elog.h> #include <intelblocks/pmclib.h> @@ -24,6 +25,85 @@ #include <soc/pci_devs.h> #include <soc/pm.h> +struct pme_status_info { +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev; +#else + struct device *dev; +#endif + uint8_t reg_offset; + uint32_t elog_event; +}; + +#define PME_STS_BIT (1 << 15) + +static void pch_log_add_elog_event(const struct pme_status_info *info) +{ + /* + * If wake source is XHCI, check for detailed wake source events on + * USB2/3 ports. + */ + if ((info->dev == PCH_DEV_XHCI) && + pch_xhci_update_wake_event(soc_get_xhci_usb_info())) + return; + + elog_add_event_wake(info->elog_event, 0); +} + +static void pch_log_pme_internal_wake_source(void) +{ + size_t i; +#ifdef __SIMPLE_DEVICE__ + pci_devfn_t dev; +#else + struct device *dev; +#endif + uint16_t val; + bool dev_found = false; + + struct pme_status_info pme_status_info[] = { + { PCH_DEV_HDA, 0x54, ELOG_WAKE_SOURCE_PME_HDA }, + { PCH_DEV_GBE, 0xcc, ELOG_WAKE_SOURCE_PME_GBE }, + { PCH_DEV_SATA, 0x74, ELOG_WAKE_SOURCE_PME_SATA }, + { PCH_DEV_CSE, 0x54, ELOG_WAKE_SOURCE_PME_CSE }, + { PCH_DEV_XHCI, 0x74, ELOG_WAKE_SOURCE_PME_XHCI }, + { PCH_DEV_USBOTG, 0x84, ELOG_WAKE_SOURCE_PME_XDCI }, + /* + * The power management control/status register is not + * listed in the cannonlake PCH EDS. We have been told + * that the PMCS register is at offset 0xCC. + */ + { PCH_DEV_CNViWIFI, 0xcc, ELOG_WAKE_SOURCE_PME_WIFI }, + }; + + for (i = 0; i < ARRAY_SIZE(pme_status_info); i++) { + dev = pme_status_info[i].dev; + if (!dev) + continue; + + val = pci_read_config16(dev, pme_status_info[i].reg_offset); + + if ((val == 0xFFFF) || !(val & PME_STS_BIT)) + continue; + + pch_log_add_elog_event(&pme_status_info[i]); + dev_found = true; + } + + /* + * If device is still not found, but the wake source is internal PME, + * try probing XHCI ports to see if any of the USB2/3 ports indicate + * that it was the wake source. This path would be taken in case of GSMI + * logging with S0ix where the pci_pm_resume_noirq runs and clears the + * PME_STS_BIT in controller register. + */ + if (!dev_found) + dev_found = pch_xhci_update_wake_event(soc_get_xhci_usb_info()); + + if (!dev_found) + elog_add_event_wake(ELOG_WAKE_SOURCE_PME_INTERNAL, 0); +} + static void pch_log_gpio_gpe(u32 gpe0_sts, u32 gpe0_en, int start) { int i; @@ -56,7 +136,7 @@ static void pch_log_wake_source(struct chipset_power_state *ps) /* XHCI - "Power Management Event Bus 0" events include XHCI */ if (ps->gpe0_sts[GPE_STD] & PME_B0_STS) - pch_xhci_update_wake_event(soc_get_xhci_usb_info()); + pch_log_pme_internal_wake_source(); /* SMBUS Wake */ if (ps->gpe0_sts[GPE_STD] & SMB_WAK_STS) |