diff options
| -rw-r--r-- | src/soc/amd/genoa/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/amd/genoa/Makefile.inc | 1 | ||||
| -rw-r--r-- | src/soc/amd/genoa/fch.c | 86 |
3 files changed, 88 insertions, 0 deletions
diff --git a/src/soc/amd/genoa/Kconfig b/src/soc/amd/genoa/Kconfig index 6cb4a8a174..f780e062de 100644 --- a/src/soc/amd/genoa/Kconfig +++ b/src/soc/amd/genoa/Kconfig @@ -28,6 +28,7 @@ config SOC_SPECIFIC_OPTIONS select SOC_AMD_COMMON_BLOCK_LPC select SOC_AMD_COMMON_BLOCK_MCAX select SOC_AMD_COMMON_BLOCK_NONCAR + select SOC_AMD_COMMON_BLOCK_PCI select SOC_AMD_COMMON_BLOCK_PCI_MMCONF select SOC_AMD_COMMON_BLOCK_PSP_GEN2 select SOC_AMD_COMMON_BLOCK_PSP_SPL diff --git a/src/soc/amd/genoa/Makefile.inc b/src/soc/amd/genoa/Makefile.inc index 54c4a27883..30efcaf4a8 100644 --- a/src/soc/amd/genoa/Makefile.inc +++ b/src/soc/amd/genoa/Makefile.inc @@ -18,6 +18,7 @@ ramstage-y += aoac.c ramstage-y += chip.c ramstage-y += cpu.c ramstage-y += domain.c +ramstage-y += fch.c ramstage-y += root_complex.c ramstage-y += smihandler.c ramstage-y += mca.c diff --git a/src/soc/amd/genoa/fch.c b/src/soc/amd/genoa/fch.c new file mode 100644 index 0000000000..f93408714b --- /dev/null +++ b/src/soc/amd/genoa/fch.c @@ -0,0 +1,86 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/acpi.h> +#include <amdblocks/acpimmio.h> +#include <amdblocks/amd_pci_util.h> +#include <amdblocks/gpio.h> +#include <amdblocks/smi.h> +#include <bootstate.h> +#include <cpu/x86/smm.h> +#include <soc/acpi.h> +#include <soc/amd_pci_int_defs.h> +#include <soc/smi.h> +#include <soc/southbridge.h> + +/* + * Table of APIC register index and associated IRQ name. Using IDX_XXX_NAME + * provides a visible association with the index, therefore helping + * maintainability of table. If a new index/name is defined in + * amd_pci_int_defs.h, just add the pair at the end of this table. + * Order is not important. + */ +static const struct irq_idx_name irq_association[] = { + { PIRQ_A, "INTA#" }, + { PIRQ_B, "INTB#" }, + { PIRQ_C, "INTC#" }, + { PIRQ_D, "INTD#" }, + { PIRQ_E, "INTE#" }, + { PIRQ_F, "INTF#/GENINT2" }, + { PIRQ_G, "INTG#" }, + { PIRQ_H, "INTH#" }, + { PIRQ_MISC, "Misc" }, + { PIRQ_MISC0, "Misc0" }, + { PIRQ_HPET_L, "HPET_L" }, + { PIRQ_HPET_H, "HPET_H" }, + { PIRQ_SIRQA, "Ser IRQ INTA" }, + { PIRQ_SIRQB, "Ser IRQ INTB" }, + { PIRQ_SIRQC, "Ser IRQ INTC" }, + { PIRQ_SIRQD, "Ser IRQ INTD" }, + { PIRQ_SCI, "SCI" }, + { PIRQ_SMBUS, "SMBUS" }, + { PIRQ_ASF, "ASF" }, + { PIRQ_PMON, "PerMon" }, + { PIRQ_SDIO, "SDIO" }, + { PIRQ_GPP0, "GPP0" }, + { PIRQ_GPP1, "GPP1" }, + { PIRQ_GPP2, "GPP2" }, + { PIRQ_GPP3, "GPP3" }, + { PIRQ_GSCI, "GEvent SCI" }, + { PIRQ_GSMI, "GEvent SMI" }, + { PIRQ_GPIO, "GPIO" }, + { PIRQ_I2C0, "I2C0" }, + { PIRQ_I2C1, "I2C1" }, + { PIRQ_I2C2, "I2C2" }, + { PIRQ_I2C3, "I2C3" }, + { PIRQ_UART0, "UART0" }, + { PIRQ_UART1, "UART1" }, + { PIRQ_I2C4, "I2C4" }, + { PIRQ_I2C5, "I2C5" }, + { PIRQ_UART2, "UART2" }, + { PIRQ_UART3, "UART3" }, +}; + +const struct irq_idx_name *sb_get_apic_reg_association(size_t *size) +{ + *size = ARRAY_SIZE(irq_association); + return irq_association; +} + +static void set_pci_irqs(void) +{ + /* Write PCI_INTR regs 0xC00/0xC01 */ + write_pci_int_table(); + + /* TODO: PIRQ configuration */ +} + +static void fch_init(void *unused) +{ + set_pci_irqs(); +} + +/* + * Hook this function into the PCI state machine on entry into BS_DEV_ENABLE. + * TODO: can this be done without using BOOT_STATE_INIT_ENTRY? + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_ENABLE, BS_ON_ENTRY, fch_init, NULL); |