diff options
| -rw-r--r-- | src/mainboard/google/brya/variants/omnigul/gpio.c | 5 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/omnigul/overridetree.cb | 21 |
2 files changed, 25 insertions, 1 deletions
diff --git a/src/mainboard/google/brya/variants/omnigul/gpio.c b/src/mainboard/google/brya/variants/omnigul/gpio.c index d3f907d21d..c0216983cb 100644 --- a/src/mainboard/google/brya/variants/omnigul/gpio.c +++ b/src/mainboard/google/brya/variants/omnigul/gpio.c @@ -316,12 +316,15 @@ static const struct pad_config romstage_gpio_table[] = { * B4 is programmed here so that it is sequenced after EN_PP3300_SSD. */ PAD_CFG_GPO(GPP_B4, 1, DEEP), - /* Enable touchscreen, hold in reset */ /* C0 : SMBCLK ==> EN_PP3300_TCHSCR */ PAD_CFG_GPO(GPP_C0, 1, DEEP), /* C1 : SMBDATA ==> USI_RST_L */ PAD_CFG_GPO(GPP_C1, 0, DEEP), + // D1 : ISH_GP1 ==> FP_RST_ODL / + PAD_CFG_GPO(GPP_D1, 0, DEEP), + // D2 : ISH_GP2 ==> EN_FP_PWR / + PAD_CFG_GPO(GPP_D2, 0, DEEP), }; const struct pad_config *variant_gpio_override_table(size_t *num) diff --git a/src/mainboard/google/brya/variants/omnigul/overridetree.cb b/src/mainboard/google/brya/variants/omnigul/overridetree.cb index b9c6d87bc3..0942299d0b 100644 --- a/src/mainboard/google/brya/variants/omnigul/overridetree.cb +++ b/src/mainboard/google/brya/variants/omnigul/overridetree.cb @@ -4,6 +4,10 @@ fw_config option STORAGE_UFS 1 option STORAGE_NVME 2 end + field FINGERPRINT 9 + option DISABLE_FP 0 + option ENABLE_FP 1 + end end chip soc/intel/alderlake @@ -318,6 +322,23 @@ chip soc/intel/alderlake device i2c 2c on end end end #I2C5 + device ref gspi1 on + chip drivers/spi/acpi + register "name" = ""CRFP"" + register "hid" = "ACPI_DT_NAMESPACE_HID" + register "uid" = "1" + register "compat_string" = ""google,cros-ec-spi"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_F15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "has_power_resource" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_D1)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D2)" + register "enable_delay_ms" = "3" + device spi 0 hidden + probe FINGERPRINT ENABLE_FP + end + end # FPMCU + end device ref pcie_rp8 off end device ref pcie_rp9 on # Enable NVMe PCIE 9 using clk 1 |