diff options
48 files changed, 119 insertions, 119 deletions
diff --git a/src/southbridge/intel/bd82x6x/finalize.c b/src/southbridge/intel/bd82x6x/finalize.c index 9c453e4611..a9cfa38c63 100644 --- a/src/southbridge/intel/bd82x6x/finalize.c +++ b/src/southbridge/intel/bd82x6x/finalize.c @@ -45,7 +45,7 @@ void intel_pch_finalize_smm(void) /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 209c8edd65..ca26250808 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -76,7 +76,7 @@ static void pch_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -285,7 +285,7 @@ static void pch_rtc_init(struct device *dev) if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) elog_add_event(ELOG_TYPE_RTC_RESET); #endif } @@ -668,7 +668,7 @@ static void southbridge_inject_dsdt(device_t dev) gnvs->ndid = gfx->ndid; memcpy(gnvs->did, gfx->did, sizeof(gnvs->did)); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) chromeos_init_vboot(&(gnvs->chromeos)); #endif diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index 0e5187c08f..70ba301c38 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -42,7 +42,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -61,7 +61,7 @@ static const char *me_bios_path_values[] = { /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -457,7 +457,7 @@ static int mkhi_get_fwcaps(void) } #endif -#if CONFIG_CHROMEOS && 0 /* DISABLED */ +#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ int mkhi_global_reset(void) { @@ -589,7 +589,7 @@ static me_bios_path intel_me_path(device_t dev) if (hfs.error_code || hfs.fpt_bad) path = ME_ERROR_BIOS_PATH; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -678,7 +678,7 @@ static int intel_me_extend_valid(device_t dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 94cec3e701..2e29233a86 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -42,7 +42,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -63,7 +63,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data); /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -424,7 +424,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section) } #endif -#if CONFIG_CHROMEOS && 0 /* DISABLED */ +#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ static int mkhi_global_reset(void) { @@ -576,7 +576,7 @@ static me_bios_path intel_me_path(device_t dev) path = ME_ERROR_BIOS_PATH; } -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -665,7 +665,7 @@ static int intel_me_extend_valid(device_t dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif @@ -706,7 +706,7 @@ static void intel_me_init(device_t dev) if (intel_me_read_mbp(&mbp_data)) break; -#if CONFIG_CHROMEOS && 0 /* DISABLED */ +#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ /* * Unlock ME in recovery mode. */ diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 1e05c9c035..0ae9826989 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -75,7 +75,7 @@ int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void gpi_route_interrupt(u8 gpi, u8 mode); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) void pch_log_state(void); #endif #else /* __PRE_RAM__ */ diff --git a/src/southbridge/intel/bd82x6x/smi.c b/src/southbridge/intel/bd82x6x/smi.c index c7cb1466ec..22489040ae 100644 --- a/src/southbridge/intel/bd82x6x/smi.c +++ b/src/southbridge/intel/bd82x6x/smi.c @@ -227,7 +227,7 @@ void southbridge_smm_init(void) u16 pm1_en; u32 gpe0_en; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) /* Log events from chipset before clearing */ pch_log_state(); #endif diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index 4cef988ef1..165acab837 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -432,7 +432,7 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -534,7 +534,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -621,7 +621,7 @@ static void southbridge_smi_apmc(void) mainboard_finalized = 1; break; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); break; @@ -645,7 +645,7 @@ static void southbridge_smi_pm1(void) // power button pressed u32 reg32; reg32 = (7 << 10) | (1 << 13); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif outl(reg32, pmbase + PM1_CNT); diff --git a/src/southbridge/intel/common/spi.c b/src/southbridge/intel/common/spi.c index 4b9bd20b2d..a6a9ae55f0 100644 --- a/src/southbridge/intel/common/spi.c +++ b/src/southbridge/intel/common/spi.c @@ -188,7 +188,7 @@ enum { SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS = 3 }; -#if CONFIG_DEBUG_SPI_FLASH +#if IS_ENABLED(CONFIG_DEBUG_SPI_FLASH) static u8 readb_(const void *addr) { diff --git a/src/southbridge/intel/common/usb_debug.c b/src/southbridge/intel/common/usb_debug.c index 23c732f52c..eeac6d92dc 100644 --- a/src/southbridge/intel/common/usb_debug.c +++ b/src/southbridge/intel/common/usb_debug.c @@ -27,7 +27,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) u32 class; pci_devfn_t dev; -#if CONFIG_HAVE_USBDEBUG_OPTIONS +#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS) if (hcd_idx==2) dev = PCI_DEV(0, 0x1a, 0); else @@ -37,7 +37,7 @@ pci_devfn_t pci_ehci_dbg_dev(unsigned int hcd_idx) #endif class = pci_read_config32(dev, PCI_CLASS_REVISION) >> 8; -#if CONFIG_HAVE_USBDEBUG_OPTIONS +#if IS_ENABLED(CONFIG_HAVE_USBDEBUG_OPTIONS) if (class != PCI_EHCI_CLASSCODE) { /* If we enter here before RCBA programming, EHCI function may * appear with the highest function number instead. diff --git a/src/southbridge/intel/fsp_bd82x6x/early_init.c b/src/southbridge/intel/fsp_bd82x6x/early_init.c index 54329c308b..f9f31348cb 100644 --- a/src/southbridge/intel/fsp_bd82x6x/early_init.c +++ b/src/southbridge/intel/fsp_bd82x6x/early_init.c @@ -151,7 +151,7 @@ static void sandybridge_setup_bars(void) outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ printk(BIOS_DEBUG, " done.\n"); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) /* Increment Boot Counter for non-S3 resume */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) @@ -160,7 +160,7 @@ static void sandybridge_setup_bars(void) printk(BIOS_DEBUG, " done.\n"); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) /* Increment Boot Counter except when resuming from S3 */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) diff --git a/src/southbridge/intel/fsp_bd82x6x/finalize.c b/src/southbridge/intel/fsp_bd82x6x/finalize.c index 22165b9b43..5b65fb0a0d 100644 --- a/src/southbridge/intel/fsp_bd82x6x/finalize.c +++ b/src/southbridge/intel/fsp_bd82x6x/finalize.c @@ -30,7 +30,7 @@ void intel_pch_finalize_smm(void) /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif diff --git a/src/southbridge/intel/fsp_bd82x6x/lpc.c b/src/southbridge/intel/fsp_bd82x6x/lpc.c index 963359f873..4a5bf68ad5 100644 --- a/src/southbridge/intel/fsp_bd82x6x/lpc.c +++ b/src/southbridge/intel/fsp_bd82x6x/lpc.c @@ -85,7 +85,7 @@ static void pch_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -295,7 +295,7 @@ static void pch_rtc_init(struct device *dev) if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) elog_add_event(ELOG_TYPE_RTC_RESET); #endif } diff --git a/src/southbridge/intel/fsp_bd82x6x/me.c b/src/southbridge/intel/fsp_bd82x6x/me.c index a634134084..a4b5f0384d 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me.c +++ b/src/southbridge/intel/fsp_bd82x6x/me.c @@ -41,7 +41,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -60,7 +60,7 @@ static const char *me_bios_path_values[] = { /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -456,7 +456,7 @@ static int mkhi_get_fwcaps(void) } #endif -#if CONFIG_CHROMEOS && 0 /* DISABLED */ +#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ int mkhi_global_reset(void) { @@ -588,7 +588,7 @@ static me_bios_path intel_me_path(device_t dev) if (hfs.error_code || hfs.fpt_bad) path = ME_ERROR_BIOS_PATH; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -677,7 +677,7 @@ static int intel_me_extend_valid(device_t dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif diff --git a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c index 4001fb9575..d89502e667 100644 --- a/src/southbridge/intel/fsp_bd82x6x/me_8.x.c +++ b/src/southbridge/intel/fsp_bd82x6x/me_8.x.c @@ -40,7 +40,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -61,7 +61,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data); /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -422,7 +422,7 @@ static void me_print_fwcaps(mbp_fw_caps *caps_section) } #endif -#if CONFIG_CHROMEOS && 0 /* DISABLED */ +#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ static int mkhi_global_reset(void) { @@ -574,7 +574,7 @@ static me_bios_path intel_me_path(device_t dev) path = ME_ERROR_BIOS_PATH; } -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -663,7 +663,7 @@ static int intel_me_extend_valid(device_t dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif @@ -704,7 +704,7 @@ static void intel_me_init(device_t dev) if (intel_me_read_mbp(&mbp_data)) break; -#if CONFIG_CHROMEOS && 0 /* DISABLED */ +#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ /* * Unlock ME in recovery mode. */ diff --git a/src/southbridge/intel/fsp_bd82x6x/pch.h b/src/southbridge/intel/fsp_bd82x6x/pch.h index 7fe40f74c7..84f21a7f92 100644 --- a/src/southbridge/intel/fsp_bd82x6x/pch.h +++ b/src/southbridge/intel/fsp_bd82x6x/pch.h @@ -67,7 +67,7 @@ int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_enable(device_t dev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) void pch_log_state(void); #endif #else diff --git a/src/southbridge/intel/fsp_bd82x6x/smi.c b/src/southbridge/intel/fsp_bd82x6x/smi.c index d97801e277..14637e62b3 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smi.c +++ b/src/southbridge/intel/fsp_bd82x6x/smi.c @@ -227,7 +227,7 @@ void southbridge_smm_init(void) u16 pm1_en; u32 gpe0_en; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) /* Log events from chipset before clearing */ pch_log_state(); #endif diff --git a/src/southbridge/intel/fsp_bd82x6x/smihandler.c b/src/southbridge/intel/fsp_bd82x6x/smihandler.c index 19337e9d14..394e0a9a1f 100644 --- a/src/southbridge/intel/fsp_bd82x6x/smihandler.c +++ b/src/southbridge/intel/fsp_bd82x6x/smihandler.c @@ -331,7 +331,7 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -433,7 +433,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -505,7 +505,7 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); break; @@ -529,7 +529,7 @@ static void southbridge_smi_pm1(void) // power button pressed u32 reg32; reg32 = (7 << 10) | (1 << 13); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif outl(reg32, pmbase + PM1_CNT); diff --git a/src/southbridge/intel/fsp_i89xx/early_init.c b/src/southbridge/intel/fsp_i89xx/early_init.c index 887bf3c2e6..7ce3c7fef5 100644 --- a/src/southbridge/intel/fsp_i89xx/early_init.c +++ b/src/southbridge/intel/fsp_i89xx/early_init.c @@ -38,7 +38,7 @@ static void sandybridge_setup_bars(void) outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ printk(BIOS_DEBUG, " done.\n"); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) /* Increment Boot Counter for non-S3 resume */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) != SLP_TYP_S3) @@ -47,7 +47,7 @@ static void sandybridge_setup_bars(void) printk(BIOS_DEBUG, " done.\n"); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) /* Increment Boot Counter except when resuming from S3 */ if ((inw(DEFAULT_PMBASE + PM1_STS) & WAK_STS) && ((inl(DEFAULT_PMBASE + PM1_CNT) >> 10) & 7) == SLP_TYP_S3) diff --git a/src/southbridge/intel/fsp_i89xx/finalize.c b/src/southbridge/intel/fsp_i89xx/finalize.c index 22165b9b43..5b65fb0a0d 100644 --- a/src/southbridge/intel/fsp_i89xx/finalize.c +++ b/src/southbridge/intel/fsp_i89xx/finalize.c @@ -30,7 +30,7 @@ void intel_pch_finalize_smm(void) /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif diff --git a/src/southbridge/intel/fsp_i89xx/lpc.c b/src/southbridge/intel/fsp_i89xx/lpc.c index 5ba296956c..8a815c5039 100644 --- a/src/southbridge/intel/fsp_i89xx/lpc.c +++ b/src/southbridge/intel/fsp_i89xx/lpc.c @@ -85,7 +85,7 @@ static void pch_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -295,7 +295,7 @@ static void pch_rtc_init(struct device *dev) if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) elog_add_event(ELOG_TYPE_RTC_RESET); #endif } diff --git a/src/southbridge/intel/fsp_i89xx/me.c b/src/southbridge/intel/fsp_i89xx/me.c index 704f209aa0..4b5a4b3ce5 100644 --- a/src/southbridge/intel/fsp_i89xx/me.c +++ b/src/southbridge/intel/fsp_i89xx/me.c @@ -41,7 +41,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -60,7 +60,7 @@ static const char *me_bios_path_values[] = { /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -555,7 +555,7 @@ static me_bios_path intel_me_path(device_t dev) if (hfs.error_code || hfs.fpt_bad) path = ME_ERROR_BIOS_PATH; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -644,7 +644,7 @@ static int intel_me_extend_valid(device_t dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif diff --git a/src/southbridge/intel/fsp_i89xx/me_8.x.c b/src/southbridge/intel/fsp_i89xx/me_8.x.c index b68a5dcfd0..b094524933 100644 --- a/src/southbridge/intel/fsp_i89xx/me_8.x.c +++ b/src/southbridge/intel/fsp_i89xx/me_8.x.c @@ -40,7 +40,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -61,7 +61,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data); /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -543,7 +543,7 @@ static me_bios_path intel_me_path(device_t dev) path = ME_ERROR_BIOS_PATH; } -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -632,7 +632,7 @@ static int intel_me_extend_valid(device_t dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif diff --git a/src/southbridge/intel/fsp_i89xx/pch.h b/src/southbridge/intel/fsp_i89xx/pch.h index 6d8b873c3e..9ae9467a7a 100644 --- a/src/southbridge/intel/fsp_i89xx/pch.h +++ b/src/southbridge/intel/fsp_i89xx/pch.h @@ -65,7 +65,7 @@ int pch_silicon_revision(void); int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_enable(device_t dev); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) void pch_log_state(void); #endif #else diff --git a/src/southbridge/intel/fsp_i89xx/romstage.c b/src/southbridge/intel/fsp_i89xx/romstage.c index c2b5221c48..385e4d6ba3 100644 --- a/src/southbridge/intel/fsp_i89xx/romstage.c +++ b/src/southbridge/intel/fsp_i89xx/romstage.c @@ -137,7 +137,7 @@ void main(FSP_INFO_HEADER *fsp_info_header) pm1_cnt = inl(DEFAULT_PMBASE + PM1_CNT); post_code(0x46); if ((pm1_sts & WAK_STS) && ((pm1_cnt >> 10) & 7) == 5) { -#if CONFIG_HAVE_ACPI_RESUME +#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) printk(BIOS_DEBUG, "Resume from S3 detected.\n"); boot_mode = 2; /* Clear SLP_TYPE. This will break stage2 but diff --git a/src/southbridge/intel/fsp_i89xx/smi.c b/src/southbridge/intel/fsp_i89xx/smi.c index f28d966431..6dc58f0b8d 100644 --- a/src/southbridge/intel/fsp_i89xx/smi.c +++ b/src/southbridge/intel/fsp_i89xx/smi.c @@ -227,7 +227,7 @@ void southbridge_smm_init(void) u16 pm1_en; u32 gpe0_en; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) /* Log events from chipset before clearing */ pch_log_state(); #endif diff --git a/src/southbridge/intel/fsp_i89xx/smihandler.c b/src/southbridge/intel/fsp_i89xx/smihandler.c index 099fb84794..ff76c20275 100644 --- a/src/southbridge/intel/fsp_i89xx/smihandler.c +++ b/src/southbridge/intel/fsp_i89xx/smihandler.c @@ -331,7 +331,7 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -433,7 +433,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -505,7 +505,7 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); break; @@ -529,7 +529,7 @@ static void southbridge_smi_pm1(void) // power button pressed u32 reg32; reg32 = (7 << 10) | (1 << 13); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif outl(reg32, pmbase + PM1_CNT); diff --git a/src/southbridge/intel/fsp_rangeley/lpc.c b/src/southbridge/intel/fsp_rangeley/lpc.c index d621a41329..cbb2297c2c 100644 --- a/src/southbridge/intel/fsp_rangeley/lpc.c +++ b/src/southbridge/intel/fsp_rangeley/lpc.c @@ -94,7 +94,7 @@ static void soc_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ write8(ibase + ILB_SERIRQ_CNTL, (1 << 7)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) write8(ibase + ILB_SERIRQ_CNTL, 0); #endif } @@ -435,7 +435,7 @@ static void southbridge_inject_dsdt(device_t dev) memset(gnvs, 0, sizeof(*gnvs)); acpi_create_gnvs(gnvs); acpi_save_gnvs((unsigned long)gnvs); -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) /* And tell SMI about it */ smm_setup_structures(gnvs, NULL, NULL); #endif diff --git a/src/southbridge/intel/fsp_rangeley/soc.h b/src/southbridge/intel/fsp_rangeley/soc.h index 0674dcae4f..4409f1e5f2 100644 --- a/src/southbridge/intel/fsp_rangeley/soc.h +++ b/src/southbridge/intel/fsp_rangeley/soc.h @@ -65,7 +65,7 @@ void soc_enable(device_t dev); #include <arch/acpi.h> void acpi_fill_in_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) void soc_log_state(void); #endif #else diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index bd0e964378..2bab05cb15 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -28,7 +28,7 @@ #endif #include "i82371eb.h" -#if CONFIG_IOAPIC +#if IS_ENABLED(CONFIG_IOAPIC) static void enable_intel_82093aa_ioapic(void) { u16 reg16; @@ -84,7 +84,7 @@ static void isa_init(struct device *dev) /* Initialize ISA DMA. */ isa_dma_init(); -#if CONFIG_IOAPIC +#if IS_ENABLED(CONFIG_IOAPIC) /* * Unlike most other southbridges the 82371EB doesn't have a built-in * IOAPIC. Instead, 82371EB-based boards that support multiple CPUs @@ -115,7 +115,7 @@ static void sb_read_resources(struct device *dev) res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED | IORESOURCE_RESERVE; -#if CONFIG_IOAPIC +#if IS_ENABLED(CONFIG_IOAPIC) res = new_resource(dev, 3); /* IOAPIC */ res->base = IO_APIC_ADDR; res->size = 0x00001000; diff --git a/src/southbridge/intel/i82801gx/lpc.c b/src/southbridge/intel/i82801gx/lpc.c index e650d823aa..a26b9f8a8e 100644 --- a/src/southbridge/intel/i82801gx/lpc.c +++ b/src/southbridge/intel/i82801gx/lpc.c @@ -329,7 +329,7 @@ static void enable_clock_gating(void) RCBA32(CG) = reg32; } -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) static void i82801gx_lock_smm(struct device *dev) { #if TEST_SMM_FLASH_LOCKDOWN @@ -448,7 +448,7 @@ static void lpc_init(struct device *dev) /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) i82801gx_lock_smm(dev); #endif diff --git a/src/southbridge/intel/i82801gx/smihandler.c b/src/southbridge/intel/i82801gx/smihandler.c index 6075db9e8b..3f537c07f0 100644 --- a/src/southbridge/intel/i82801gx/smihandler.c +++ b/src/southbridge/intel/i82801gx/smihandler.c @@ -414,7 +414,7 @@ static void southbridge_smi_sleep(unsigned int node, smm_state_save_area_t *stat printk(BIOS_DEBUG, "SMI#: ERROR: SLP_TYP reserved\n"); break; } -#if !CONFIG_SMM_TSEG +#if !IS_ENABLED(CONFIG_SMM_TSEG) /* Unlock the SMI semaphore. We're currently in SMM, and the semaphore * will never be unlocked because the next outl will switch off the CPU. * This might open a small race between the smi_release_lock() and the outl() diff --git a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl b/src/southbridge/intel/i82801ix/acpi/sleepstates.asl index 62bb0264de..d7fb2a56bb 100644 --- a/src/southbridge/intel/i82801ix/acpi/sleepstates.asl +++ b/src/southbridge/intel/i82801ix/acpi/sleepstates.asl @@ -15,7 +15,7 @@ */ Name(\_S0, Package(){0x0,0x0,0x0,0x0}) -#if !CONFIG_HAVE_ACPI_RESUME +#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) Name(\_S1, Package(){0x1,0x0,0x0,0x0}) #else Name(\_S3, Package(){0x5,0x0,0x0,0x0}) diff --git a/src/southbridge/intel/i82801ix/i82801ix.c b/src/southbridge/intel/i82801ix/i82801ix.c index 0f3a08c9cf..7d44fba88b 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.c +++ b/src/southbridge/intel/i82801ix/i82801ix.c @@ -222,7 +222,7 @@ static void i82801ix_init(void *chip_info) i82801ix_hide_functions(); /* Reset watchdog timer. */ -#if !CONFIG_HAVE_SMI_HANDLER +#if !IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) outw(0x0008, DEFAULT_TCOBASE + 0x12); /* Set higher timer value. */ #endif outw(0x0000, DEFAULT_TCOBASE + 0x00); /* Update timer. */ diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index 8212b0a092..bc45b9ddc1 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -369,7 +369,7 @@ static void enable_clock_gating(void) RCBA32(0x38c0) |= 7; } -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) static void i82801ix_lock_smm(struct device *dev) { #if TEST_SMM_FLASH_LOCKDOWN @@ -464,7 +464,7 @@ static void lpc_init(struct device *dev) /* Interrupt 9 should be level triggered (SCI) */ i8259_configure_irq_trigger(9, 1); -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) i82801ix_lock_smm(dev); #endif } diff --git a/src/southbridge/intel/ibexpeak/lpc.c b/src/southbridge/intel/ibexpeak/lpc.c index f01d8b20c0..a152dfe8b9 100644 --- a/src/southbridge/intel/ibexpeak/lpc.c +++ b/src/southbridge/intel/ibexpeak/lpc.c @@ -71,7 +71,7 @@ static void pch_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -280,7 +280,7 @@ static void pch_rtc_init(struct device *dev) if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) elog_add_event(ELOG_TYPE_RTC_RESET); #endif } diff --git a/src/southbridge/intel/ibexpeak/me.c b/src/southbridge/intel/ibexpeak/me.c index da6bfa81f5..70dbcbf54f 100644 --- a/src/southbridge/intel/ibexpeak/me.c +++ b/src/southbridge/intel/ibexpeak/me.c @@ -41,7 +41,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -60,7 +60,7 @@ static const char *me_bios_path_values[] = { /* MMIO base address for MEI interface */ static u32 *mei_base_address; -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -470,7 +470,7 @@ static me_bios_path intel_me_path(device_t dev) if (hfs.error_code || hfs.fpt_bad) path = ME_ERROR_BIOS_PATH; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -559,7 +559,7 @@ static int intel_me_extend_valid(device_t dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif diff --git a/src/southbridge/intel/ibexpeak/pch.h b/src/southbridge/intel/ibexpeak/pch.h index d87f8e0b47..63307d9368 100644 --- a/src/southbridge/intel/ibexpeak/pch.h +++ b/src/southbridge/intel/ibexpeak/pch.h @@ -70,7 +70,7 @@ int pch_silicon_type(void); int pch_silicon_supported(int type, int rev); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); void gpi_route_interrupt(u8 gpi, u8 mode); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) void pch_log_state(void); #endif #else /* __PRE_RAM__ */ diff --git a/src/southbridge/intel/ibexpeak/smi.c b/src/southbridge/intel/ibexpeak/smi.c index 961f3d5598..9f6badb224 100644 --- a/src/southbridge/intel/ibexpeak/smi.c +++ b/src/southbridge/intel/ibexpeak/smi.c @@ -228,7 +228,7 @@ void southbridge_smm_init(void) u16 pm1_en; u32 gpe0_en; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) /* Log events from chipset before clearing */ pch_log_state(); #endif diff --git a/src/southbridge/intel/ibexpeak/smihandler.c b/src/southbridge/intel/ibexpeak/smihandler.c index af25c49ceb..08cf3b7fe1 100644 --- a/src/southbridge/intel/ibexpeak/smihandler.c +++ b/src/southbridge/intel/ibexpeak/smihandler.c @@ -433,7 +433,7 @@ static void southbridge_smi_sleep(void) /* Do any mainboard sleep handling */ mainboard_smi_sleep(slp_typ); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -535,7 +535,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -607,7 +607,7 @@ static void southbridge_smi_apmc(void) printk(BIOS_DEBUG, "SMI#: Setting GNVS to %p\n", gnvs); } break; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); break; @@ -631,7 +631,7 @@ static void southbridge_smi_pm1(void) // power button pressed u32 reg32; reg32 = (7 << 10) | (1 << 13); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif outl(reg32, pmbase + PM1_CNT); diff --git a/src/southbridge/intel/lynxpoint/acpi/pch.asl b/src/southbridge/intel/lynxpoint/acpi/pch.asl index c30bfa47dd..fbbd26d66f 100644 --- a/src/southbridge/intel/lynxpoint/acpi/pch.asl +++ b/src/southbridge/intel/lynxpoint/acpi/pch.asl @@ -96,7 +96,7 @@ Scope(\) #include "smbus.asl" // Serial IO -#if CONFIG_INTEL_LYNXPOINT_LP +#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) #include "serialio.asl" #include "lpt_lp.asl" #endif diff --git a/src/southbridge/intel/lynxpoint/early_pch.c b/src/southbridge/intel/lynxpoint/early_pch.c index 0e4fa3d5ea..cb4bc7efb6 100644 --- a/src/southbridge/intel/lynxpoint/early_pch.c +++ b/src/southbridge/intel/lynxpoint/early_pch.c @@ -24,7 +24,7 @@ #include "pch.h" #include "chip.h" -#if CONFIG_INTEL_LYNXPOINT_LP +#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) #include "lp_gpio.h" #else #include "southbridge/intel/common/gpio.h" @@ -133,7 +133,7 @@ int early_pch_init(const void *gpio_map, pch_enable_bars(); -#if CONFIG_INTEL_LYNXPOINT_LP +#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) setup_pch_lp_gpios(gpio_map); #else setup_pch_gpios(gpio_map); @@ -154,7 +154,7 @@ int early_pch_init(const void *gpio_map, wake_from_s3 = sleep_type_s3(); -#if CONFIG_ELOG_BOOT_COUNT +#if IS_ENABLED(CONFIG_ELOG_BOOT_COUNT) if (!wake_from_s3) boot_count_increment(); #endif diff --git a/src/southbridge/intel/lynxpoint/finalize.c b/src/southbridge/intel/lynxpoint/finalize.c index 79a0915671..e95872be3c 100644 --- a/src/southbridge/intel/lynxpoint/finalize.c +++ b/src/southbridge/intel/lynxpoint/finalize.c @@ -34,7 +34,7 @@ void intel_pch_finalize_smm(void) /* Lock SPIBAR */ RCBA32_OR(0x3804, (1 << 15)); -#if CONFIG_SPI_FLASH_SMM +#if IS_ENABLED(CONFIG_SPI_FLASH_SMM) /* Re-init SPI driver to handle locked BAR */ spi_init(); #endif diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c index ff78ea9eeb..b43ca329b6 100644 --- a/src/southbridge/intel/lynxpoint/lpc.c +++ b/src/southbridge/intel/lynxpoint/lpc.c @@ -77,7 +77,7 @@ static void pch_enable_serial_irqs(struct device *dev) /* Set packet length and toggle silent mode bit for one frame. */ pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (1 << 6) | ((21 - 17) << 2) | (0 << 0)); -#if !CONFIG_SERIRQ_CONTINUOUS_MODE +#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE) pci_write_config8(dev, SERIRQ_CNTL, (1 << 7) | (0 << 6) | ((21 - 17) << 2) | (0 << 0)); #endif @@ -292,7 +292,7 @@ static void pch_rtc_init(struct device *dev) if (rtc_failed) { reg8 &= ~RTC_BATTERY_DEAD; pci_write_config8(dev, GEN_PMCON_3, reg8); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) elog_add_event(ELOG_TYPE_RTC_RESET); #endif } @@ -498,7 +498,7 @@ static void enable_lp_clock_gating(device_t dev) static void pch_set_acpi_mode(void) { -#if CONFIG_HAVE_SMI_HANDLER +#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) if (!acpi_is_wakeup_s3()) { #if ENABLE_ACPI_MODE_IN_COREBOOT printk(BIOS_DEBUG, "Enabling ACPI via APMC:\n"); @@ -760,7 +760,7 @@ static void southbridge_inject_dsdt(device_t dev) gnvs->mpen = 1; /* Enable Multi Processing */ gnvs->pcnt = dev_count_cpu(); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) chromeos_init_vboot(&(gnvs->chromeos)); #endif diff --git a/src/southbridge/intel/lynxpoint/me_9.x.c b/src/southbridge/intel/lynxpoint/me_9.x.c index 355db4b6e1..c393feb377 100644 --- a/src/southbridge/intel/lynxpoint/me_9.x.c +++ b/src/southbridge/intel/lynxpoint/me_9.x.c @@ -37,7 +37,7 @@ #include "me.h" #include "pch.h" -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) #include <vendorcode/google/chromeos/chromeos.h> #include <vendorcode/google/chromeos/gnvs.h> #endif @@ -59,7 +59,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev); static u32 *mei_base_address; void intel_me_mbp_clear(device_t dev); -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) static void mei_dump(void *ptr, int dword, int offset, const char *type) { struct mei_csr *csr; @@ -519,7 +519,7 @@ static void me_print_fwcaps(mbp_mefwcaps *cap) #endif /* CONFIG_DEBUG_INTEL_ME */ #endif -#if CONFIG_CHROMEOS && 0 /* DISABLED */ +#if IS_ENABLED(CONFIG_CHROMEOS) && 0 /* DISABLED */ /* Tell ME to issue a global reset */ static int mkhi_global_reset(void) { @@ -579,7 +579,7 @@ void intel_me_finalize_smm(void) if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0) return; -#if CONFIG_ME_MBP_CLEAR_LATE +#if IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE) /* Wait for ME MBP Cleared indicator */ intel_me_mbp_clear(PCH_ME_DEV); #endif @@ -707,7 +707,7 @@ static me_bios_path intel_me_path(device_t dev) path = ME_ERROR_BIOS_PATH; } -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) if (path != ME_NORMAL_BIOS_PATH) { struct elog_event_data_me_extended data = { .current_working_state = hfs.working_state, @@ -796,7 +796,7 @@ static int intel_me_extend_valid(device_t dev) } printk(BIOS_DEBUG, "\n"); -#if CONFIG_CHROMEOS +#if IS_ENABLED(CONFIG_CHROMEOS) /* Save hash in NVS for the OS to verify */ chromeos_set_me_hash(extend, count); #endif @@ -835,7 +835,7 @@ static void intel_me_init(device_t dev) #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) me_print_fw_version(mbp_data.fw_version_name); -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) me_print_fwcaps(mbp_data.fw_capabilities); #endif @@ -991,7 +991,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) host.interrupt_generate = 1; write_host_csr(&host); -#if !CONFIG_ME_MBP_CLEAR_LATE +#if !IS_ENABLED(CONFIG_ME_MBP_CLEAR_LATE) /* Wait for the mbp_cleared indicator. */ intel_me_mbp_clear(dev); #endif @@ -1000,7 +1000,7 @@ static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev) #if (CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_DEBUG) printk(BIOS_INFO, "ME MBP: Header: items: %d, size dw: %d\n", mbp->header.num_entries, mbp->header.mbp_size); -#if CONFIG_DEBUG_INTEL_ME +#if IS_ENABLED(CONFIG_DEBUG_INTEL_ME) for (i = 0; i < mbp->header.mbp_size - 1; i++) { printk(BIOS_INFO, "ME MBP: %04x: 0x%08x\n", i, mbp->data[i]); } diff --git a/src/southbridge/intel/lynxpoint/pch.h b/src/southbridge/intel/lynxpoint/pch.h index 655aef1353..c9c9c32acd 100644 --- a/src/southbridge/intel/lynxpoint/pch.h +++ b/src/southbridge/intel/lynxpoint/pch.h @@ -72,7 +72,7 @@ #define SMBUS_IO_BASE 0x0400 #define SMBUS_SLAVE_ADDR 0x24 -#if CONFIG_INTEL_LYNXPOINT_LP +#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) #define DEFAULT_PMBASE 0x1000 #define DEFAULT_GPIOBASE 0x1400 #define DEFAULT_GPIOSIZE 0x400 @@ -181,7 +181,7 @@ void pch_disable_devfn(device_t dev); u32 pch_iobp_read(u32 address); void pch_iobp_write(u32 address, u32 data); void pch_iobp_update(u32 address, u32 andvalue, u32 orvalue); -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) void pch_log_state(void); #endif void acpi_create_intel_hpet(acpi_hpet_t * hpet); diff --git a/src/southbridge/intel/lynxpoint/pmutil.c b/src/southbridge/intel/lynxpoint/pmutil.c index d895c56df1..b14c1f7c91 100644 --- a/src/southbridge/intel/lynxpoint/pmutil.c +++ b/src/southbridge/intel/lynxpoint/pmutil.c @@ -26,7 +26,7 @@ #include <console/console.h> #include "pch.h" -#if CONFIG_INTEL_LYNXPOINT_LP +#if IS_ENABLED(CONFIG_INTEL_LYNXPOINT_LP) #include "lp_gpio.h" #endif diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 8c9cb58cbf..5f1bdf76fa 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -29,7 +29,7 @@ void southbridge_smm_clear_state(void) { u32 smi_en; -#if CONFIG_ELOG +#if IS_ENABLED(CONFIG_ELOG) /* Log events from chipset before clearing */ pch_log_state(); #endif @@ -123,7 +123,7 @@ void smm_setup_structures(void *gnvs, void *tcg, void *smi1) /* * Finalize system before payload boot if not in ChromeOS environment. */ -#if !CONFIG_CHROMEOS +#if !IS_ENABLED(CONFIG_CHROMEOS) static void finalize_boot(void *unused) { diff --git a/src/southbridge/intel/lynxpoint/smihandler.c b/src/southbridge/intel/lynxpoint/smihandler.c index 0102308812..37a7a2b6a7 100644 --- a/src/southbridge/intel/lynxpoint/smihandler.c +++ b/src/southbridge/intel/lynxpoint/smihandler.c @@ -130,13 +130,13 @@ static void southbridge_smi_sleep(void) mainboard_smi_sleep(slp_typ); /* USB sleep preparations */ -#if !CONFIG_FINALIZE_USB_ROUTE_XHCI +#if !IS_ENABLED(CONFIG_FINALIZE_USB_ROUTE_XHCI) usb_ehci_sleep_prepare(PCH_EHCI1_DEV, slp_typ); usb_ehci_sleep_prepare(PCH_EHCI2_DEV, slp_typ); #endif usb_xhci_sleep_prepare(PCH_XHCI_DEV, slp_typ); -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) /* Log S3, S4, and S5 entry */ if (slp_typ >= ACPI_S3) elog_add_event_byte(ELOG_TYPE_ACPI_ENTER, slp_typ); @@ -243,7 +243,7 @@ static em64t101_smm_state_save_area_t *smi_apmc_find_state_save(u8 cmd) return NULL; } -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) static void southbridge_smi_gsmi(void) { u32 *ret, *param; @@ -314,7 +314,7 @@ static void southbridge_smi_apmc(void) case 0xca: usb_xhci_route_all(); break; -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) case ELOG_GSMI_APM_CNT: southbridge_smi_gsmi(); break; @@ -333,7 +333,7 @@ static void southbridge_smi_pm1(void) */ if (pm1_sts & PWRBTN_STS) { // power button pressed -#if CONFIG_ELOG_GSMI +#if IS_ENABLED(CONFIG_ELOG_GSMI) elog_add_event(ELOG_TYPE_POWER_BUTTON); #endif disable_pm1_control(-1UL); |