diff options
30 files changed, 72 insertions, 39 deletions
diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 8b227bd7e4..8db932ce58 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -19,6 +19,10 @@ config DCACHE_RAM_SIZE hex default 0x4000 # 16 kB +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + config DCACHE_RAM_BASE hex default 0xfeffc000 # 4GB - 16MB - DCACHE_RAM_SIZE diff --git a/src/cpu/intel/socket_LGA775/Makefile.inc b/src/cpu/intel/socket_LGA775/Makefile.inc index ceb084c900..a7984a9dfb 100644 --- a/src/cpu/intel/socket_LGA775/Makefile.inc +++ b/src/cpu/intel/socket_LGA775/Makefile.inc @@ -13,7 +13,14 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep +ifneq ($(CONFIG_C_ENVIRONMENT_BOOTBLOCK),y) cpu_incs-y += $(src)/cpu/intel/car/p4-netburst/cache_as_ram.S +else +bootblock-y += ../car/p4-netburst/cache_as_ram.S +bootblock-y += ../car/bootblock.c +bootblock-y += ../../x86/early_reset.S +endif + postcar-y += ../car/p4-netburst/exit_car.S romstage-y += ../car/romstage.c diff --git a/src/mainboard/asrock/g41c-gs/Makefile.inc b/src/mainboard/asrock/g41c-gs/Makefile.inc index 82e72fbb81..ab352cb73d 100644 --- a/src/mainboard/asrock/g41c-gs/Makefile.inc +++ b/src/mainboard/asrock/g41c-gs/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/g41c-gs/romstage.c b/src/mainboard/asrock/g41c-gs/early_init.c index 06e13eb652..c7c7b730a6 100644 --- a/src/mainboard/asrock/g41c-gs/romstage.c +++ b/src/mainboard/asrock/g41c-gs/early_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pnp_ops.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -27,7 +28,7 @@ #define SERIAL_DEV_R1 PNP_DEV(0x2e, W83627DHG_SP1) #define SUPERIO_DEV PNP_DEV(0x2e, 0) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { /* Set GPIOs on superio, enable UART */ if (CONFIG(SUPERIO_NUVOTON_NCT6776)) { diff --git a/src/mainboard/asus/p5qc/Makefile.inc b/src/mainboard/asus/p5qc/Makefile.inc index 5c1d211ca7..88c57200d9 100644 --- a/src/mainboard/asus/p5qc/Makefile.inc +++ b/src/mainboard/asus/p5qc/Makefile.inc @@ -13,5 +13,8 @@ CONFIG_GPIO_C:=$(call strip_quotes, $(CONFIG_GPIO_C)) +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-y += cstates.c romstage-y += $(CONFIG_GPIO_C) diff --git a/src/mainboard/asus/p5qc/romstage.c b/src/mainboard/asus/p5qc/early_init.c index 53aa176b38..cbc84ba101 100644 --- a/src/mainboard/asus/p5qc/romstage.c +++ b/src/mainboard/asus/p5qc/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <southbridge/intel/i82801jx/i82801jx.h> #include <northbridge/intel/x4x/x4x.h> #include <superio/winbond/w83667hg-a/w83667hg-a.h> @@ -21,7 +22,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { /* TODO? */ RCBA32(RCBA_CG) = 0xbf7f001f; diff --git a/src/mainboard/asus/p5ql-em/Makefile.inc b/src/mainboard/asus/p5ql-em/Makefile.inc index 641e18f136..ba881b7eeb 100644 --- a/src/mainboard/asus/p5ql-em/Makefile.inc +++ b/src/mainboard/asus/p5ql-em/Makefile.inc @@ -11,6 +11,9 @@ # GNU General Public License for more details. # +bootblock-y += early_init.c + romstage-y += gpio.c +romstage-y += early_init.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p5ql-em/romstage.c b/src/mainboard/asus/p5ql-em/early_init.c index fa22a645d4..38038012f7 100644 --- a/src/mainboard/asus/p5ql-em/romstage.c +++ b/src/mainboard/asus/p5ql-em/early_init.c @@ -12,6 +12,7 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pnp_ops.h> #include <console/console.h> #include <northbridge/intel/x4x/x4x.h> @@ -24,7 +25,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/asus/p5qpl-am/Makefile.inc b/src/mainboard/asus/p5qpl-am/Makefile.inc index 82e72fbb81..ab352cb73d 100644 --- a/src/mainboard/asus/p5qpl-am/Makefile.inc +++ b/src/mainboard/asus/p5qpl-am/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += variants/$(VARIANT_DIR)/gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asus/p5qpl-am/romstage.c b/src/mainboard/asus/p5qpl-am/early_init.c index ad16c0f72a..5987033a09 100644 --- a/src/mainboard/asus/p5qpl-am/romstage.c +++ b/src/mainboard/asus/p5qpl-am/early_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <cf9_reset.h> #include <device/pnp_ops.h> #include <console/console.h> @@ -27,7 +28,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/foxconn/g41s-k/Makefile.inc b/src/mainboard/foxconn/g41s-k/Makefile.inc index ca8de4d597..161c623eaa 100644 --- a/src/mainboard/foxconn/g41s-k/Makefile.inc +++ b/src/mainboard/foxconn/g41s-k/Makefile.inc @@ -1,6 +1,9 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/ diff --git a/src/mainboard/foxconn/g41s-k/romstage.c b/src/mainboard/foxconn/g41s-k/early_init.c index b4bd77d78b..454b1ea0b0 100644 --- a/src/mainboard/foxconn/g41s-k/romstage.c +++ b/src/mainboard/foxconn/g41s-k/early_init.c @@ -16,6 +16,7 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <superio/ite/common/ite.h> @@ -24,7 +25,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8720F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8720F_GPIO) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { /* Set up GPIOs on Super I/O. */ ite_reg_write(GPIO_DEV, 0x25, 0x01); diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc index 0786d6fca5..4100476891 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc +++ b/src/mainboard/gigabyte/ga-g41m-es2l/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c index bde4f33bef..4540d4e03d 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/romstage.c +++ b/src/mainboard/gigabyte/ga-g41m-es2l/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pci_ops.h> #include <southbridge/intel/i82801gx/i82801gx.h> #include <northbridge/intel/x4x/x4x.h> @@ -29,7 +30,7 @@ * We should use standard gpio.h eventually */ -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { pci_devfn_t dev; diff --git a/src/mainboard/intel/dg41wv/Makefile.inc b/src/mainboard/intel/dg41wv/Makefile.inc index 0786d6fca5..4100476891 100644 --- a/src/mainboard/intel/dg41wv/Makefile.inc +++ b/src/mainboard/intel/dg41wv/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/dg41wv/romstage.c b/src/mainboard/intel/dg41wv/early_init.c index ff018af5f6..3cb40955d0 100644 --- a/src/mainboard/intel/dg41wv/romstage.c +++ b/src/mainboard/intel/dg41wv/early_init.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <device/pnp_ops.h> #include <northbridge/intel/x4x/x4x.h> #include <southbridge/intel/i82801gx/i82801gx.h> @@ -23,7 +24,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { /* Set GPIOs on superio, enable UART */ pnp_enter_ext_func_mode(SERIAL_DEV); diff --git a/src/mainboard/intel/dg43gt/Makefile.inc b/src/mainboard/intel/dg43gt/Makefile.inc index 6b3d94a037..f89d1302e3 100644 --- a/src/mainboard/intel/dg43gt/Makefile.inc +++ b/src/mainboard/intel/dg43gt/Makefile.inc @@ -14,4 +14,7 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/intel/dg43gt/romstage.c b/src/mainboard/intel/dg43gt/early_init.c index 71fd87ad74..8457707ba1 100644 --- a/src/mainboard/intel/dg43gt/romstage.c +++ b/src/mainboard/intel/dg43gt/early_init.c @@ -14,6 +14,7 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <southbridge/intel/i82801jx/i82801jx.h> #include <northbridge/intel/x4x/x4x.h> #include <superio/winbond/w83627dhg/w83627dhg.h> @@ -21,7 +22,7 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { RCBA32(0x3410) = 0x00060464; RCBA32(RCBA_BUC) &= ~BUC_LAND; diff --git a/src/mainboard/lenovo/thinkcentre_a58/Makefile.inc b/src/mainboard/lenovo/thinkcentre_a58/Makefile.inc index 0786d6fca5..4100476891 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/Makefile.inc +++ b/src/mainboard/lenovo/thinkcentre_a58/Makefile.inc @@ -1,4 +1,7 @@ ramstage-y += cstates.c romstage-y += gpio.c +bootblock-y += early_init.c +romstage-y += early_init.c + ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/lenovo/thinkcentre_a58/romstage.c b/src/mainboard/lenovo/thinkcentre_a58/early_init.c index 5594cbdda6..a8f6443948 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/romstage.c +++ b/src/mainboard/lenovo/thinkcentre_a58/early_init.c @@ -15,12 +15,13 @@ * GNU General Public License for more details. */ +#include <bootblock_common.h> #include <northbridge/intel/x4x/x4x.h> #include <superio/smsc/smscsuperio/smscsuperio.h> #define SERIAL_DEV PNP_DEV(0x2e, SMSCSUPERIO_SP1) -void mb_lpc_setup(void) +void bootblock_mainboard_early_init(void) { smscsuperio_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/northbridge/intel/x4x/Kconfig b/src/northbridge/intel/x4x/Kconfig index 8f002c6a8f..2a54e2495e 100644 --- a/src/northbridge/intel/x4x/Kconfig +++ b/src/northbridge/intel/x4x/Kconfig @@ -26,15 +26,12 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_GMA_ACPI select CACHE_MRC_SETTINGS select PARALLEL_MP + select C_ENVIRONMENT_BOOTBLOCK config CBFS_SIZE hex default 0x100000 if !SOUTHBRIDGE_INTEL_I82801GX -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "northbridge/intel/x4x/bootblock.c" - config VGA_BIOS_ID string default "8086,2e32" diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index 79a03cb77e..cde7121f93 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -16,6 +16,8 @@ ifeq ($(CONFIG_NORTHBRIDGE_INTEL_X4X),y) +bootblock-y += bootblock.c + romstage-y += early_init.c romstage-y += raminit.c romstage-y += raminit_ddr23.c diff --git a/src/northbridge/intel/x4x/bootblock.c b/src/northbridge/intel/x4x/bootblock.c index e733287e93..64643dd79c 100644 --- a/src/northbridge/intel/x4x/bootblock.c +++ b/src/northbridge/intel/x4x/bootblock.c @@ -15,13 +15,11 @@ */ #include <device/pci_ops.h> +#include <cpu/intel/car/bootblock.h> +#include "x4x.h" #include "iomap.h" -/* Just re-define these instead of including x4x.h. It blows up romcc. */ -#define D0F0_PCIEXBAR_LO 0x60 -#define D0F0_PCIEXBAR_HI 0x64 - -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg32; diff --git a/src/northbridge/intel/x4x/romstage.c b/src/northbridge/intel/x4x/romstage.c index c3a503643f..eae87f3674 100644 --- a/src/northbridge/intel/x4x/romstage.c +++ b/src/northbridge/intel/x4x/romstage.c @@ -34,16 +34,6 @@ void mainboard_romstage_entry(void) u8 boot_path = 0; u8 s3_resume; -#if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) - i82801jx_lpc_setup(); -#elif CONFIG(SOUTHBRIDGE_INTEL_I82801GX) - i82801gx_lpc_setup(); -#endif - - mb_lpc_setup(); - - console_init(); - enable_smbus(); #if CONFIG(SOUTHBRIDGE_INTEL_I82801JX) diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index e4a6c215d8..aaaa28aeac 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -373,7 +373,6 @@ enum ddr2_signals { void x4x_early_init(void); void x4x_late_init(int s3resume); -void mb_lpc_setup(void); void mb_get_spd_map(u8 spd_map[4]); void mb_pre_raminit_setup(int s3_resume); u32 decode_igd_memory_size(u32 gms); diff --git a/src/southbridge/intel/i82801jx/Kconfig b/src/southbridge/intel/i82801jx/Kconfig index eeb843e910..7f44fcfc1d 100644 --- a/src/southbridge/intel/i82801jx/Kconfig +++ b/src/southbridge/intel/i82801jx/Kconfig @@ -51,9 +51,4 @@ config INTEL_DESCRIPTOR_MODE_REQUIRED config HPET_MIN_TICKS hex default 0x80 - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "southbridge/intel/i82801jx/bootblock.c" - endif diff --git a/src/southbridge/intel/i82801jx/Makefile.inc b/src/southbridge/intel/i82801jx/Makefile.inc index 30ed351970..1527b8adb0 100644 --- a/src/southbridge/intel/i82801jx/Makefile.inc +++ b/src/southbridge/intel/i82801jx/Makefile.inc @@ -16,6 +16,9 @@ ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82801JX),y) +bootblock-y += bootblock.c +bootblock-y += early_init.c + ramstage-y += i82801jx.c ramstage-y += pci.c ramstage-y += lpc.c diff --git a/src/southbridge/intel/i82801jx/bootblock.c b/src/southbridge/intel/i82801jx/bootblock.c index 01faef34af..b6016793c2 100644 --- a/src/southbridge/intel/i82801jx/bootblock.c +++ b/src/southbridge/intel/i82801jx/bootblock.c @@ -14,6 +14,7 @@ */ #include <device/pci_ops.h> +#include <cpu/intel/car/bootblock.h> #include "i82801jx.h" static void enable_spi_prefetch(void) @@ -29,14 +30,14 @@ static void enable_spi_prefetch(void) pci_write_config8(dev, 0xdc, reg8); } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { enable_spi_prefetch(); - /* Enable RCBA */ - pci_write_config32(PCI_DEV(0, 0x1f, 0), RCBA, - (uintptr_t)DEFAULT_RCBA | 1); + i82801jx_setup_bars(); /* Enable upper 128bytes of CMOS. */ RCBA32(0x3400) = (1 << 2); + + i82801jx_lpc_setup(); } diff --git a/src/southbridge/intel/i82801jx/early_init.c b/src/southbridge/intel/i82801jx/early_init.c index 469073240e..1afc6b365f 100644 --- a/src/southbridge/intel/i82801jx/early_init.c +++ b/src/southbridge/intel/i82801jx/early_init.c @@ -56,7 +56,7 @@ void i82801jx_lpc_setup(void) pci_write_config32(d31f0, D31F0_GEN4_DEC, config->gen4_dec); } -static void i82801jx_setup_bars(void) +void i82801jx_setup_bars(void) { const pci_devfn_t d31f0 = PCI_DEV(0, 0x1f, 0); diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index d406d1d631..26a99f42f7 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -235,6 +235,7 @@ int smbus_block_write(unsigned int device, unsigned int cmd, u8 bytes, const u8 *buf); #endif void i82801jx_lpc_setup(void); +void i82801jx_setup_bars(void); void i82801jx_early_init(void); #endif |