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-rw-r--r--src/mainboard/purism/librem_cnl/Kconfig4
-rw-r--r--src/mainboard/purism/librem_cnl/devicetree.cb103
-rw-r--r--src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb (renamed from src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb)85
-rw-r--r--src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb (renamed from src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb)84
4 files changed, 105 insertions, 171 deletions
diff --git a/src/mainboard/purism/librem_cnl/Kconfig b/src/mainboard/purism/librem_cnl/Kconfig
index 919462299f..39b0883a53 100644
--- a/src/mainboard/purism/librem_cnl/Kconfig
+++ b/src/mainboard/purism/librem_cnl/Kconfig
@@ -32,8 +32,8 @@ config VARIANT_DIR
default "librem_mini" if BOARD_PURISM_LIBREM_MINI || BOARD_PURISM_LIBREM_MINI_V2
default "librem_14" if BOARD_PURISM_LIBREM_14
-config DEVICETREE
- default "variants/\$(CONFIG_VARIANT_DIR)/devicetree.cb"
+config OVERRIDE_DEVICETREE
+ default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
config CBFS_SIZE
default 0x800000 if BOARD_PURISM_LIBREM_MINI
diff --git a/src/mainboard/purism/librem_cnl/devicetree.cb b/src/mainboard/purism/librem_cnl/devicetree.cb
new file mode 100644
index 0000000000..a1fc9e11c5
--- /dev/null
+++ b/src/mainboard/purism/librem_cnl/devicetree.cb
@@ -0,0 +1,103 @@
+chip soc/intel/cannonlake
+
+ # Enable Enhanced Intel SpeedStep
+ register "eist_enable" = "1"
+
+# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
+ register "SaGv" = "SaGv_Enabled"
+
+# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
+
+ # Acoustic Noise
+ register "AcousticNoiseMitigation" = "1"
+
+ register "FastPkgCRampDisableIa" = "1"
+ register "FastPkgCRampDisableGt" = "1"
+ register "FastPkgCRampDisableSa" = "1"
+ register "FastPkgCRampDisableFivr" = "1"
+
+ register "SlowSlewRateForIa" = "3" # fast/16
+ register "SlowSlewRateForGt" = "3" # fast/16
+ register "SlowSlewRateForSa" = "3" # fast/16
+ register "SlowSlewRateForFivr" = "3" # fast/16
+
+ # Power
+ register "PchPmSlpS3MinAssert" = "3" # 50ms
+ register "PchPmSlpS4MinAssert" = "1" # 1s
+ register "PchPmSlpSusMinAssert" = "2" # 500ms
+ register "PchPmSlpAMinAssert" = "4" # 2s
+
+ # Thermal
+ register "tcc_offset" = "10"
+
+# PM Util (soc/intel/cannonlake/pmutil.c)
+ # GPE configuration
+ # Note that GPE events called out in ASL code rely on this
+ # route. i.e. If this route changes then the affected GPE
+ # offset bits also need to be changed.
+ # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
+ register "gpe0_dw0" = "PMC_GPP_C"
+ register "gpe0_dw1" = "PMC_GPP_D"
+ register "gpe0_dw2" = "PMC_GPP_E"
+
+# Actual device tree
+ device cpu_cluster 0 on
+ device lapic 0 on end
+ end
+
+ device domain 0 on
+ device pci 00.0 on end # Host Bridge
+ device pci 02.0 on end # Integrated Graphics Device
+ device pci 04.0 on # SA Thermal device
+ register "Device4Enable" = "1"
+ end
+ device pci 12.0 on end # Thermal Subsystem
+ device pci 13.0 off end # Integrated Sensor Hub
+ device pci 14.0 on end # USB xHC
+ device pci 14.1 off end # USB xDCI (OTG)
+ device pci 15.0 off end # I2C #0
+ device pci 15.1 off end # I2C #1
+ device pci 15.2 off end # I2C #2
+ device pci 15.3 off end # I2C #3
+ device pci 16.0 off end # Management Engine Interface 1
+ device pci 16.1 off end # Management Engine Interface 2
+ device pci 16.2 off end # Management Engine IDE-R
+ device pci 16.3 off end # Management Engine KT Redirection
+ device pci 16.4 off end # Management Engine Interface 3
+ device pci 16.5 off end # Management Engine Interface 4
+ device pci 17.0 on end # SATA
+ device pci 19.0 off end # I2C #4
+ device pci 19.1 off end # I2C #5
+ device pci 19.2 off end # UART #2
+ device pci 1a.0 off end # eMMC
+ device pci 1c.0 off end # PCI Express Port 1
+ device pci 1c.1 off end # PCI Express Port 2
+ device pci 1c.2 off end # PCI Express Port 3
+ device pci 1c.3 off end # PCI Express Port 4
+ device pci 1c.4 off end # PCI Express Port 5
+ device pci 1c.5 off end # PCI Express Port 6
+ device pci 1c.6 off end # PCI Express Port 7
+ device pci 1c.7 off end # PCI Express Port 8
+ device pci 1d.0 off end # PCI Express Port 9
+ device pci 1d.1 off end # PCI Express Port 10
+ device pci 1d.2 off end # PCI Express Port 11
+ device pci 1d.3 off end # PCI Express Port 12
+ device pci 1d.4 off end # PCI Express Port 13
+ device pci 1d.5 off end # PCI Express Port 14
+ device pci 1d.6 off end # PCI Express Port 15
+ device pci 1d.7 off end # PCI Express Port 16
+ device pci 1e.0 off end # UART #0
+ device pci 1e.1 off end # UART #1
+ device pci 1e.2 off end # GSPI #0
+ device pci 1e.3 off end # GSPI #1
+ device pci 1f.0 on end # LPC Bridge
+ device pci 1f.1 off end # P2SB
+ device pci 1f.2 hidden end # Power Management Controller
+ device pci 1f.3 on # Intel HDA
+ register "PchHdaAudioLinkHda" = "1"
+ end
+ device pci 1f.4 on end # SMBus
+ device pci 1f.5 on end # PCH SPI
+ device pci 1f.6 off end # GbE
+ end
+end
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
index 8b5c9086b9..b979740f8d 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_14/devicetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_14/overridetree.cb
@@ -15,12 +15,6 @@ chip soc/intel/cannonlake
.tdp_pl2_override = 20,
}"
- # Enable Enhanced Intel SpeedStep
- register "eist_enable" = "1"
-
-# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
- register "SaGv" = "SaGv_Enabled"
-
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
# Serial I/O
@@ -28,45 +22,8 @@ chip soc/intel/cannonlake
[PchSerialIoIndexI2C0] = PchSerialIoPci,
}"
- # Acoustic Noise
- register "AcousticNoiseMitigation" = "1"
-
- register "FastPkgCRampDisableIa" = "1"
- register "FastPkgCRampDisableGt" = "1"
- register "FastPkgCRampDisableSa" = "1"
- register "FastPkgCRampDisableFivr" = "1"
-
- register "SlowSlewRateForIa" = "3" # fast/16
- register "SlowSlewRateForGt" = "3" # fast/16
- register "SlowSlewRateForSa" = "3" # fast/16
- register "SlowSlewRateForFivr" = "3" # fast/16
-
- # Power
- register "PchPmSlpS3MinAssert" = "3" # 50ms
- register "PchPmSlpS4MinAssert" = "1" # 1s
- register "PchPmSlpSusMinAssert" = "2" # 500ms
- register "PchPmSlpAMinAssert" = "4" # 2s
-
- # Thermal
- register "tcc_offset" = "10"
-
-# PM Util (soc/intel/cannonlake/pmutil.c)
- # GPE configuration
- # Note that GPE events called out in ASL code rely on this
- # route. i.e. If this route changes then the affected GPE
- # offset bits also need to be changed.
- # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
- register "gpe0_dw0" = "PMC_GPP_C"
- register "gpe0_dw1" = "PMC_GPP_D"
- register "gpe0_dw2" = "PMC_GPP_E"
-
# Actual device tree
- device cpu_cluster 0 on
- device lapic 0 on end
- end
-
device domain 0 on
- device pci 00.0 on end # Host Bridge
device pci 02.0 on # Integrated Graphics Device
register "gfx" = "GMA_DEFAULT_PANEL(0)"
register "panel_cfg" = "{
@@ -78,11 +35,6 @@ chip soc/intel/cannonlake
.backlight_off_delay_ms = 1,
}"
end
- device pci 04.0 on # SA Thermal device
- register "Device4Enable" = "1"
- end
- device pci 12.0 on end # Thermal Subsystem
- device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI
chip drivers/usb/acpi
device usb 0.0 on
@@ -189,15 +141,6 @@ chip soc/intel/cannonlake
device i2c 2c on end
end
end
- device pci 15.1 off end # I2C #1
- device pci 15.2 off end # I2C #2
- device pci 15.3 off end # I2C #3
- device pci 16.0 off end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
- device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA
register "satapwroptimize" = "1"
register "SataSalpSupport" = "1"
@@ -208,16 +151,6 @@ chip soc/intel/cannonlake
register "SataPortsEnable[2]" = "1"
register "SataPortsDevSlp[2]" = "1"
end
- device pci 19.0 off end # I2C #4
- device pci 19.1 off end # I2C #5
- device pci 19.2 off end # UART #2
- device pci 1a.0 off end # eMMC
- device pci 1c.0 off end # PCI Express Port 1
- device pci 1c.1 off end # PCI Express Port 2
- device pci 1c.2 off end # PCI Express Port 3
- device pci 1c.3 off end # PCI Express Port 4
- device pci 1c.4 off end # PCI Express Port 5
- device pci 1c.5 off end # PCI Express Port 6
device pci 1c.6 on # PCI Express Port 7 -- x1 M.2/E 2230 (WLAN)
register "PcieRpEnable[6]" = "1"
register "PcieRpSlotImplemented[6]" = "1"
@@ -241,9 +174,6 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[0]" = "0"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe)
register "PcieRpEnable[12]" = "1"
register "PcieRpSlotImplemented[12]" = "1"
@@ -252,13 +182,6 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[1]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
- device pci 1d.5 off end # PCI Express Port 14
- device pci 1d.6 off end # PCI Express Port 15
- device pci 1d.7 off end # PCI Express Port 16
- device pci 1e.0 off end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 off end # GSPI #0
- device pci 1e.3 off end # GSPI #1
device pci 1f.0 on # LPC Bridge
# LPC configuration from lspci -s 1f.0 -xxx
# Address 0x88: Decode 0x68 - 0x6F (EC PM channel)
@@ -271,13 +194,5 @@ chip soc/intel/cannonlake
device pnp 0c31.0 on end
end
end
- device pci 1f.1 off end # P2SB
- device pci 1f.2 hidden end # Power Management Controller
- device pci 1f.3 on # Intel HDA
- register "PchHdaAudioLinkHda" = "1"
- end
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
- device pci 1f.6 off end # GbE
end
end
diff --git a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
index 08d152c574..927031373e 100644
--- a/src/mainboard/purism/librem_cnl/variants/librem_mini/devicetree.cb
+++ b/src/mainboard/purism/librem_cnl/variants/librem_mini/overridetree.cb
@@ -7,62 +7,19 @@ chip soc/intel/cannonlake
.tdp_pl2_override = 28,
}"
- # Enable Enhanced Intel SpeedStep
- register "eist_enable" = "1"
-
# FSP Memory (soc/intel/cannonlake/romstage/fsp_params.c)
register "SaGv" = "SaGv_FixedHigh"
# FSP Silicon (soc/intel/cannonlake/fsp_params.c)
- # Misc
- register "AcousticNoiseMitigation" = "1"
-
- register "FastPkgCRampDisableIa" = "1"
- register "FastPkgCRampDisableGt" = "1"
- register "FastPkgCRampDisableSa" = "1"
- register "FastPkgCRampDisableFivr" = "1"
-
- register "SlowSlewRateForIa" = "3" # fast/16
- register "SlowSlewRateForGt" = "3" # fast/16
- register "SlowSlewRateForSa" = "3" # fast/16
- register "SlowSlewRateForFivr" = "3" # fast/16
-
- # Power
- register "PchPmSlpS3MinAssert" = "3" # 50ms
- register "PchPmSlpS4MinAssert" = "1" # 1s
- register "PchPmSlpSusMinAssert" = "2" # 500ms
- register "PchPmSlpAMinAssert" = "4" # 2s
-
# Thermal
register "tcc_offset" = "12"
# Serial IRQ Mode
register "serirq_mode" = "SERIRQ_CONTINUOUS"
-# PM Util (soc/intel/cannonlake/pmutil.c)
- # GPE configuration
- # Note that GPE events called out in ASL code rely on this
- # route. i.e. If this route changes then the affected GPE
- # offset bits also need to be changed.
- # sudo devmem2 0xfe001920 (pmc_bar + GPIO_GPE_CFG)
- register "gpe0_dw0" = "PMC_GPP_C"
- register "gpe0_dw1" = "PMC_GPP_D"
- register "gpe0_dw2" = "PMC_GPP_E"
-
# Actual device tree
- device cpu_cluster 0 on
- device lapic 0 on end
- end
-
device domain 0 on
- device pci 00.0 on end # Host Bridge
- device pci 02.0 on end # Integrated Graphics Device
- device pci 04.0 on # SA Thermal device
- register "Device4Enable" = "1"
- end
- device pci 12.0 on end # Thermal Subsystem
- device pci 13.0 off end # Integrated Sensor Hub
device pci 14.0 on # USB xHCI
chip drivers/usb/acpi
device usb 0.0 on
@@ -166,33 +123,11 @@ chip soc/intel/cannonlake
register "usb3_ports[4]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear lower
register "usb3_ports[5]" = "USB3_PORT_DEFAULT(OC2)" # Type-A rear upper
end
- device pci 14.1 off end # USB xDCI (OTG)
- device pci 15.0 off end # I2C #0
- device pci 15.1 off end # I2C #1
- device pci 15.2 off end # I2C #2
- device pci 15.3 off end # I2C #3
- device pci 16.0 off end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
- device pci 16.5 off end # Management Engine Interface 4
device pci 17.0 on # SATA
register "SataPortsEnable[0]" = "1" # 2.5"
register "SataPortsEnable[2]" = "1" # m.2
register "satapwroptimize" = "1"
end
- device pci 19.0 off end # I2C #4
- device pci 19.1 off end # I2C #5
- device pci 19.2 off end # UART #2
- device pci 1a.0 off end # eMMC
- device pci 1c.0 off end # PCI Express Port 1
- device pci 1c.1 off end # PCI Express Port 2
- device pci 1c.2 off end # PCI Express Port 3
- device pci 1c.3 off end # PCI Express Port 4
- device pci 1c.4 off end # PCI Express Port 5
- device pci 1c.5 off end # PCI Express Port 6
- device pci 1c.6 off end # PCI Express Port 7
device pci 1c.7 on # PCI Express Port 8 -- x1 M.2/E 2230 (WLAN)
register "PcieRpSlotImplemented[7]" = "1"
register "PcieRpEnable[7]" = "1"
@@ -201,15 +136,12 @@ chip soc/intel/cannonlake
register "PcieClkSrcUsage[2]" = "0x80"
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthOther" "M.2/E 2230" "SlotDataBusWidth1X"
end
- device pci 1d.0 off end # PCI Express Port 9
device pci 1d.1 on # PCI Express Port 10
device pci 00.0 on end # x1 (LAN)
register "PcieRpEnable[9]" = "1"
register "PcieClkSrcUsage[3]" = "9"
register "PcieClkSrcClkReq[3]" = "3"
end
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
device pci 1d.4 on # PCI Express Port 13 -- x4 M.2/M 2280 (NVMe)
register "PcieRpSlotImplemented[12]" = "1"
register "PcieRpEnable[12]" = "1"
@@ -218,21 +150,5 @@ chip soc/intel/cannonlake
register "PcieClkSrcClkReq[1]" = "1"
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
end
- device pci 1d.5 off end # PCI Express Port 14
- device pci 1d.6 off end # PCI Express Port 15
- device pci 1d.7 off end # PCI Express Port 16
- device pci 1e.0 off end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 off end # GSPI #0
- device pci 1e.3 off end # GSPI #1
- device pci 1f.0 on end # LPC Bridge
- device pci 1f.1 off end # P2SB
- device pci 1f.2 hidden end # Power Management Controller
- device pci 1f.3 on # Intel HDA
- register "PchHdaAudioLinkHda" = "1"
- end
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
- device pci 1f.6 off end # GbE
end
end
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-27 01:11:27 +0000