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-rw-r--r--src/soc/amd/cezanne/romstage.c2
-rw-r--r--src/soc/amd/common/block/apob/Makefile.inc1
-rw-r--r--src/soc/amd/common/block/apob/apob_cache.c4
-rw-r--r--src/soc/amd/common/block/include/amdblocks/apob_cache.h1
-rw-r--r--src/soc/amd/picasso/romstage.c2
5 files changed, 4 insertions, 6 deletions
diff --git a/src/soc/amd/cezanne/romstage.c b/src/soc/amd/cezanne/romstage.c
index b64fb4bbe5..9e863c3966 100644
--- a/src/soc/amd/cezanne/romstage.c
+++ b/src/soc/amd/cezanne/romstage.c
@@ -2,7 +2,6 @@
#include <acpi/acpi.h>
#include <amdblocks/acpimmio.h>
-#include <amdblocks/apob_cache.h>
#include <amdblocks/memmap.h>
#include <amdblocks/pmlib.h>
#include <arch/cpu.h>
@@ -25,7 +24,6 @@ asmlinkage void car_stage_entry(void)
fill_chipset_state();
fsp_memory_init(acpi_is_wakeup_s3());
- soc_update_apob_cache();
/* Fixup settings FSP-M should not be changing */
fch_disable_legacy_dma_io();
diff --git a/src/soc/amd/common/block/apob/Makefile.inc b/src/soc/amd/common/block/apob/Makefile.inc
index 16baf81813..6e217df648 100644
--- a/src/soc/amd/common/block/apob/Makefile.inc
+++ b/src/soc/amd/common/block/apob/Makefile.inc
@@ -1,3 +1,4 @@
ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_APOB),y)
romstage-y += apob_cache.c
+ramstage-y += apob_cache.c
endif # CONFIG_SOC_AMD_COMMON_BLOCK_APOB
diff --git a/src/soc/amd/common/block/apob/apob_cache.c b/src/soc/amd/common/block/apob/apob_cache.c
index 34d54727fc..c41627b7ac 100644
--- a/src/soc/amd/common/block/apob/apob_cache.c
+++ b/src/soc/amd/common/block/apob/apob_cache.c
@@ -4,6 +4,7 @@
#include <amdblocks/apob_cache.h>
#include <assert.h>
#include <boot_device.h>
+#include <bootstate.h>
#include <commonlib/region.h>
#include <console/console.h>
#include <fmap.h>
@@ -96,7 +97,7 @@ static void *get_apob_from_nv_region(struct region *region)
}
/* Save APOB buffer to flash */
-void soc_update_apob_cache(void)
+static void soc_update_apob_cache(void *unused)
{
struct apob_base_header *apob_rom;
struct region_device write_rdev;
@@ -183,3 +184,4 @@ void *soc_fill_apob_cache(void)
*/
return get_apob_nv_address();
}
+BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, soc_update_apob_cache, NULL);
diff --git a/src/soc/amd/common/block/include/amdblocks/apob_cache.h b/src/soc/amd/common/block/include/amdblocks/apob_cache.h
index 1d29ddc279..79228e5de2 100644
--- a/src/soc/amd/common/block/include/amdblocks/apob_cache.h
+++ b/src/soc/amd/common/block/include/amdblocks/apob_cache.h
@@ -4,6 +4,5 @@
#define AMD_BLOCK_APOB_CACHE_H
void *soc_fill_apob_cache(void);
-void soc_update_apob_cache(void);
#endif /* AMD_BLOCK_APOB_CACHE_H */
diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c
index d3ceec587f..197241084f 100644
--- a/src/soc/amd/picasso/romstage.c
+++ b/src/soc/amd/picasso/romstage.c
@@ -1,7 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <acpi/acpi.h>
-#include <amdblocks/apob_cache.h>
#include <amdblocks/memmap.h>
#include <amdblocks/pmlib.h>
#include <arch/cpu.h>
@@ -27,7 +26,6 @@ asmlinkage void car_stage_entry(void)
post_code(0x43);
fsp_memory_init(acpi_is_wakeup_s3());
- soc_update_apob_cache();
memmap_stash_early_dram_usage();