diff options
| -rw-r--r-- | src/cpu/intel/model_206ax/bootblock.c | 67 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x230/cmos.default | 1 | ||||
| -rw-r--r-- | src/mainboard/lenovo/x230/cmos.layout | 3 | ||||
| -rw-r--r-- | src/southbridge/intel/bd82x6x/pch.h | 1 |
4 files changed, 53 insertions, 19 deletions
diff --git a/src/cpu/intel/model_206ax/bootblock.c b/src/cpu/intel/model_206ax/bootblock.c index cfbe8aee3d..bc07b14f3f 100644 --- a/src/cpu/intel/model_206ax/bootblock.c +++ b/src/cpu/intel/model_206ax/bootblock.c @@ -6,6 +6,7 @@ #include <cpu/x86/msr.h> #include <halt.h> #include <stdint.h> +#include <option.h> #include "model_206ax.h" @@ -17,34 +18,29 @@ #error "CPU must be paired with Intel BD82X6X or C216 southbridge" #endif -static void set_flex_ratio_to_tdp_nominal(void) +static u32 set_flex_ratio_to_tdp_nominal(u32 soft_reset) { msr_t flex_ratio, msr; - u32 soft_reset; u8 nominal_ratio; /* Minimum CPU revision for configurable TDP support */ if (cpuid_eax(1) < IVB_CONFIG_TDP_MIN_CPUID) - return; + return soft_reset; /* Check for Flex Ratio support */ flex_ratio = rdmsr(MSR_FLEX_RATIO); if (!(flex_ratio.lo & FLEX_RATIO_EN)) - return; + return soft_reset; /* Check for >0 configurable TDPs */ msr = rdmsr(MSR_PLATFORM_INFO); if (((msr.hi >> 1) & 3) == 0) - return; + return soft_reset; /* Use nominal TDP ratio for flex ratio */ msr = rdmsr(MSR_CONFIG_TDP_NOMINAL); nominal_ratio = msr.lo & 0xff; - /* See if flex ratio is already set to nominal TDP ratio */ - if (((flex_ratio.lo >> 8) & 0xff) == nominal_ratio) - return; - /* Set flex ratio to nominal TDP ratio */ flex_ratio.lo &= ~0xff00; flex_ratio.lo |= nominal_ratio << 8; @@ -53,22 +49,55 @@ static void set_flex_ratio_to_tdp_nominal(void) /* Set flex ratio in soft reset data register bits 11:6. * RCBA region is enabled in southbridge bootblock */ - soft_reset = RCBA32(SOFT_RESET_DATA); soft_reset &= ~(0x3f << 6); soft_reset |= (nominal_ratio & 0x3f) << 6; - RCBA32(SOFT_RESET_DATA) = soft_reset; + return soft_reset; +} + +static u32 set_hyperthreading_option(u32 soft_reset) +{ + struct cpuid_result result; + unsigned int ht_requested; + + ht_requested = get_uint_option("hyper_threading", 1); + + /* Make sure the CPU has more than one logical processor per core */ + result = cpuid_ext(0xb, 1); + if ((result.ebx & 0xff) == 1) + return soft_reset; + + soft_reset &= ~1; + soft_reset |= !ht_requested; /* Bit 0 is HT disable */ + return soft_reset; +} + +static void soft_reset_settings(void) +{ + int need_reset; + u32 soft_reset; + + soft_reset = RCBA32(SOFT_RESET_DATA); + soft_reset = set_flex_ratio_to_tdp_nominal(soft_reset); + soft_reset = set_hyperthreading_option(soft_reset); - /* Set soft reset control to use register value */ - RCBA32_OR(SOFT_RESET_CTRL, 1); + /* Check if we didn't already request these settings */ + need_reset = !(RCBA32(SOFT_RESET_CTRL) & 1) || + RCBA32(SOFT_RESET_DATA) != soft_reset; - /* Issue warm reset, will be "CPU only" due to soft reset data */ - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); + if (need_reset) { + /* Set current requests */ + RCBA32(SOFT_RESET_DATA) = soft_reset; + /* Use them instead of defaults */ + RCBA32_OR(SOFT_RESET_CTRL, 1); + outb(0x0, 0xcf9); + outb(0x6, 0xcf9); + halt(); + } else { + RCBA32_OR(SOFT_RESET_LOCK, 1); + } } void bootblock_early_cpu_init(void) { - /* Set flex ratio and reset if needed */ - set_flex_ratio_to_tdp_nominal(); + soft_reset_settings(); } diff --git a/src/mainboard/lenovo/x230/cmos.default b/src/mainboard/lenovo/x230/cmos.default index 732e214b32..089039caf6 100644 --- a/src/mainboard/lenovo/x230/cmos.default +++ b/src/mainboard/lenovo/x230/cmos.default @@ -18,3 +18,4 @@ backlight=Both usb_always_on=Disable f1_to_f12_as_primary=Enable me_state=Normal +hyper_threading=Enable diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 22110189a1..b7068e5be9 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -39,6 +39,9 @@ entries 425 1 e 13 me_state 426 2 h 0 me_state_prev +# coreboot config options: cpu +428 1 e 1 hyper_threading + # coreboot config options: northbridge 432 3 e 11 gfx_uma_size diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 2fb97f0d60..917dc87c1b 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -307,6 +307,7 @@ void early_usb_init(void); #define D22IR 0x315c /* 16bit */ #define D20IR 0x3160 /* 16bit */ #define OIC 0x31fe /* 16bit */ +#define SOFT_RESET_LOCK 0x38f0 #define SOFT_RESET_CTRL 0x38f4 #define SOFT_RESET_DATA 0x38f8 |