diff options
| -rw-r--r-- | src/soc/intel/meteorlake/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/meteorlake/fsp_params.c | 8 |
2 files changed, 8 insertions, 1 deletions
diff --git a/src/soc/intel/meteorlake/Kconfig b/src/soc/intel/meteorlake/Kconfig index 8f4e3a2405..6391ed8d8d 100644 --- a/src/soc/intel/meteorlake/Kconfig +++ b/src/soc/intel/meteorlake/Kconfig @@ -187,6 +187,7 @@ config IED_REGION_SIZE config HEAP_SIZE hex + default 0x80000 if BMP_LOGO default 0x10000 # Intel recommends reserving the PCIe TBT root port resources as below: diff --git a/src/soc/intel/meteorlake/fsp_params.c b/src/soc/intel/meteorlake/fsp_params.c index 7a2a9d8b48..7a7a2e60c2 100644 --- a/src/soc/intel/meteorlake/fsp_params.c +++ b/src/soc/intel/meteorlake/fsp_params.c @@ -10,6 +10,7 @@ #include <device/pci.h> #include <fsp/api.h> #include <fsp/fsp_debug_event.h> +#include <fsp/fsp_gop_blt.h> #include <fsp/ppi/mp_service_ppi.h> #include <fsp/util.h> #include <option.h> @@ -868,5 +869,10 @@ __weak void mainboard_silicon_init_params(FSP_S_CONFIG *s_cfg) /* Handle FSP logo params */ void soc_load_logo(FSPS_UPD *supd) { - bmp_load_logo(&supd->FspsConfig.LogoPtr, &supd->FspsConfig.LogoSize); + fsp_convert_bmp_to_gop_blt(&supd->FspsConfig.LogoPtr, + &supd->FspsConfig.LogoSize, + &supd->FspsConfig.BltBufferAddress, + &supd->FspsConfig.BltBufferSize, + &supd->FspsConfig.LogoPixelHeight, + &supd->FspsConfig.LogoPixelWidth); } |