diff options
| -rw-r--r-- | src/superio/ite/it8718f/it8718f.h | 1 | ||||
| -rw-r--r-- | src/superio/ite/it8718f/it8718f_early_serial.c | 14 |
2 files changed, 15 insertions, 0 deletions
diff --git a/src/superio/ite/it8718f/it8718f.h b/src/superio/ite/it8718f/it8718f.h index 1967d25b5f..c441db3fbd 100644 --- a/src/superio/ite/it8718f/it8718f.h +++ b/src/superio/ite/it8718f/it8718f.h @@ -32,6 +32,7 @@ #if defined(__PRE_RAM__) && !defined(__ROMCC__) void it8718f_24mhz_clkin(void); +void it8718f_disable_reboot(void); void it8718f_enable_serial(device_t dev, unsigned iobase); #endif diff --git a/src/superio/ite/it8718f/it8718f_early_serial.c b/src/superio/ite/it8718f/it8718f_early_serial.c index fabbde5e8f..c3a8c73264 100644 --- a/src/superio/ite/it8718f/it8718f_early_serial.c +++ b/src/superio/ite/it8718f/it8718f_early_serial.c @@ -74,6 +74,20 @@ void it8718f_24mhz_clkin(void) it8718f_exit_conf(); } +/* GIGABYTE uses a special SuperIO register to protect its Dual BIOS + * mechanism. It lives in the GPIO LDN. However, register 0xEF is not + * mentioned in the IT8718F datasheet so just hardcode it to 0x7E for + * now. + */ +void it8718f_disable_reboot(void) +{ + it8718f_enter_conf(); + + it8718f_sio_write(0x07, 0xEF, 0x7E); + + it8718f_exit_conf(); +} + /* Enable the peripheral devices on the IT8718F Super I/O chip. */ void it8718f_enable_serial(device_t dev, unsigned iobase) { |