diff options
| -rw-r--r-- | src/soc/intel/xeon_sp/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/finalize.c | 14 | ||||
| -rw-r--r-- | src/soc/intel/xeon_sp/include/soc/pmc.h | 2 |
3 files changed, 17 insertions, 0 deletions
diff --git a/src/soc/intel/xeon_sp/Kconfig b/src/soc/intel/xeon_sp/Kconfig index fa8403a235..94fed021f9 100644 --- a/src/soc/intel/xeon_sp/Kconfig +++ b/src/soc/intel/xeon_sp/Kconfig @@ -36,6 +36,7 @@ config CPU_SPECIFIC_OPTIONS select FSP_M_XIP select POSTCAR_STAGE select PARALLEL_MP_AP_WORK + select PM_ACPI_TIMER_OPTIONAL select PMC_GLOBAL_RESET_ENABLE_LOCK select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/xeon_sp/finalize.c b/src/soc/intel/xeon_sp/finalize.c index 044c1cc138..76e3ef1125 100644 --- a/src/soc/intel/xeon_sp/finalize.c +++ b/src/soc/intel/xeon_sp/finalize.c @@ -7,6 +7,7 @@ #include <device/pci.h> #include <intelpch/lockdown.h> #include <soc/pci_devs.h> +#include <soc/pm.h> #include <soc/util.h> #include "chip.h" @@ -26,6 +27,19 @@ static void soc_finalize(void *unused) { printk(BIOS_DEBUG, "Finalizing chipset.\n"); + /* + * Disable ACPI PM timer based on Kconfig + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO. + * + * Note: In contrast to other platforms supporting PM timer emulation, + * disabling the PM timer must be done *after* FSP has run on Xeon-SP, + * because FSP makes use of the PM timer. + */ + if (!CONFIG(USE_PM_ACPI_TIMER)) + setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); + apm_control(APM_CNT_FINALIZE); lock_pam0123(); diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index bbdb60bb4b..69299b6057 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -36,6 +36,8 @@ /* Memory mapped IO registers in PMC */ #define PMSYNC_TPR_CFG 0xc8 #define PMSYNC_LOCK (1 << 15) +#define PCH_PWRM_ACPI_TMR_CTL 0xfc +#define ACPI_TIM_DIS (1 << 1) #define GPIO_GPE_CFG 0x120 #define GPE0_DWX_MASK 0xf #define GPE0_DW_SHIFT(x) (4 * (x)) |