diff options
| -rw-r--r-- | src/soc/intel/cannonlake/pmc.c | 9 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/Kconfig | 1 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/include/soc/pmc.h | 2 | ||||
| -rw-r--r-- | src/soc/intel/denverton_ns/pmc.c | 11 | ||||
| -rw-r--r-- | src/soc/intel/skylake/pmc.c | 9 |
5 files changed, 32 insertions, 0 deletions
diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index d502e0675a..4c88685d04 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -118,6 +118,15 @@ static void soc_pmc_init(struct device *dev) * found. */ pmc_set_acpi_mode(); + + /* + * Disable ACPI PM timer based on Kconfig + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO. + */ + if (!CONFIG(USE_PM_ACPI_TIMER)) + setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); } static void pmc_fill_ssdt(const struct device *dev) diff --git a/src/soc/intel/denverton_ns/Kconfig b/src/soc/intel/denverton_ns/Kconfig index a578a71fd0..a8ed92be28 100644 --- a/src/soc/intel/denverton_ns/Kconfig +++ b/src/soc/intel/denverton_ns/Kconfig @@ -25,6 +25,7 @@ config CPU_SPECIFIC_OPTIONS select HAVE_SMI_HANDLER select CACHE_MRC_SETTINGS select PCR_COMMON_IOSF_1_0 + select PM_ACPI_TIMER_OPTIONAL select SUPPORT_CPU_UCODE_IN_CBFS select INTEL_DESCRIPTOR_MODE_CAPABLE select SOC_INTEL_COMMON_BLOCK diff --git a/src/soc/intel/denverton_ns/include/soc/pmc.h b/src/soc/intel/denverton_ns/include/soc/pmc.h index fdb1028f1f..0ba24fcb2f 100644 --- a/src/soc/intel/denverton_ns/include/soc/pmc.h +++ b/src/soc/intel/denverton_ns/include/soc/pmc.h @@ -240,6 +240,8 @@ #define GPIO_GPE_CFG 0x120 #define GPE0_DWX_MASK 0x7 #define GPE0_DW_SHIFT(x) (4 + 4*(x)) +#define PCH_PWRM_ACPI_TMR_CTL 0xfc +#define ACPI_TIM_DIS (1 << 1) /* I/O ports */ #define RST_CNT 0xcf9 diff --git a/src/soc/intel/denverton_ns/pmc.c b/src/soc/intel/denverton_ns/pmc.c index d75f7f05a6..2c208d2aa5 100644 --- a/src/soc/intel/denverton_ns/pmc.c +++ b/src/soc/intel/denverton_ns/pmc.c @@ -4,6 +4,7 @@ #include <device/pci_ops.h> #include <console/console.h> #include <device/device.h> +#include <device/mmio.h> #include <device/pci.h> #include <device/pci_ids.h> @@ -46,6 +47,16 @@ static void pmc_init(struct device *dev) /* Configure ACPI mode. */ pch_set_acpi_mode(); + + /* + * Disable ACPI PM timer based on Kconfig + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO. + */ + if (!CONFIG(USE_PM_ACPI_TIMER)) + setbits8((volatile void *)(uintptr_t)(pwrm_base + PCH_PWRM_ACPI_TMR_CTL), + ACPI_TIM_DIS); } static void pci_pmc_read_resources(struct device *dev) diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index c2e724f353..b9b85c2e8f 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -101,6 +101,15 @@ void pmc_soc_init(struct device *dev) pci_or_config32(dev, GEN_PMCON_B, 0); setbits32(pwrmbase + GBLRST_CAUSE0, 0); setbits32(pwrmbase + GBLRST_CAUSE1, 0); + + /* + * Disable ACPI PM timer based on Kconfig + * + * Disabling ACPI PM timer is necessary for XTAL OSC shutdown. + * Disabling ACPI PM timer also switches off TCO. + */ + if (!CONFIG(USE_PM_ACPI_TIMER)) + setbits8(pmc_mmio_regs() + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); } static void pm1_enable_pwrbtn_smi(void *unused) |