diff options
| -rw-r--r-- | src/arch/armv7/coreboot_ram.ld | 7 | ||||
| -rw-r--r-- | src/cpu/samsung/exynos5250/Kconfig | 9 | ||||
| -rw-r--r-- | src/mainboard/google/snow/ramstage.c | 8 |
3 files changed, 8 insertions, 16 deletions
diff --git a/src/arch/armv7/coreboot_ram.ld b/src/arch/armv7/coreboot_ram.ld index c69499c362..0644e3669d 100644 --- a/src/arch/armv7/coreboot_ram.ld +++ b/src/arch/armv7/coreboot_ram.ld @@ -26,7 +26,7 @@ ENTRY(_start) SECTIONS { - . = CONFIG_RAMBASE; + . = CONFIG_SYS_SDRAM_BASE; /* First we place the code and read only data (typically const declared). * This could theoretically be placed in rom. */ @@ -123,11 +123,6 @@ SECTIONS _ram_seg = _text; _eram_seg = _eheap; - /* CONFIG_RAMTOP is the upper address of cached memory (among other - * things). We must not exceed beyond that address, there be dragons. - */ - _bogus = ASSERT( ( _eram_seg < (CONFIG_RAMTOP)) , "Please increase CONFIG_RAMTOP"); - /* Discard the sections we don't need/want */ /DISCARD/ : { diff --git a/src/cpu/samsung/exynos5250/Kconfig b/src/cpu/samsung/exynos5250/Kconfig index f62195a3b0..2869d7689e 100644 --- a/src/cpu/samsung/exynos5250/Kconfig +++ b/src/cpu/samsung/exynos5250/Kconfig @@ -90,11 +90,6 @@ config SYS_TEXT_BASE hex "Executable code section" default 0x43e00000 -config RAMBASE +config COREBOOT_TABLES_SIZE hex - default SYS_SDRAM_BASE -# according to stefan, this is RAMBASE + 1M. -config RAMTOP - hex - default 0x40100000 - + default 0x100000 diff --git a/src/mainboard/google/snow/ramstage.c b/src/mainboard/google/snow/ramstage.c index d280dbe050..b779999c51 100644 --- a/src/mainboard/google/snow/ramstage.c +++ b/src/mainboard/google/snow/ramstage.c @@ -30,9 +30,11 @@ void main(void) printk(BIOS_INFO, "hello from ramstage\n"); #if CONFIG_WRITE_HIGH_TABLES - /* Leave some space for ACPI tables */ - high_tables_base = CONFIG_RAMBASE; - high_tables_size = CONFIG_RAMBASE + 0x100000; + /* place at top of physical memory */ + high_tables_size = CONFIG_COREBOOT_TABLES_SIZE; + high_tables_base = CONFIG_SYS_SDRAM_BASE + + ((CONFIG_DRAM_SIZE_MB * 1024) * CONFIG_NR_DRAM_BANKS) - + CONFIG_COREBOOT_TABLES_SIZE; #endif hardwaremain(0); |