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-rw-r--r--src/mainboard/system76/bonw14/devicetree.cb80
1 files changed, 19 insertions, 61 deletions
diff --git a/src/mainboard/system76/bonw14/devicetree.cb b/src/mainboard/system76/bonw14/devicetree.cb
index aa7d1abb5e..918a0b8cd4 100644
--- a/src/mainboard/system76/bonw14/devicetree.cb
+++ b/src/mainboard/system76/bonw14/devicetree.cb
@@ -56,8 +56,7 @@ chip soc/intel/cannonlake
device domain 0 on
subsystemid 0x1558 0x7714 inherit
- device pci 00.0 on end # Host Bridge
- device pci 01.0 on # GPU Port
+ device ref peg0 on
# PCI Express Graphics #0 x16, Clock 7 (NVIDIA GPU)
register "PcieClkSrcUsage[7]" = "0x40"
register "PcieClkSrcClkReq[7]" = "7"
@@ -67,14 +66,9 @@ chip soc/intel/cannonlake
device pci 00.2 on end # USB xHCI Host controller
device pci 00.3 on end # USB Type-C UCSI controller
end
- # TODO: is this enough to disable iGPU?
- device pci 02.0 off end # Integrated Graphics Device
- device pci 04.0 on end # SA Thermal device
- device pci 12.0 on end # Thermal Subsystem
- device pci 12.5 off end # UFS SCS
- device pci 12.6 off end # GSPI #2
- device pci 13.0 off end # Integrated Sensor Hub
- device pci 14.0 on # USB xHCI
+ device ref dptf on end
+ device ref thermal on end
+ device ref xhci on
register "usb2_ports" = "{
[0] = USB2_PORT_MID(OC_SKIP), /* USB 3_2 */
[1] = USB2_PORT_MID(OC_SKIP), /* USB 3_1 */
@@ -95,15 +89,14 @@ chip soc/intel/cannonlake
[3] = USB3_PORT_DEFAULT(OC_SKIP), /* USB 3_3 */
}"
end
- device pci 14.2 on end # Shared SRAM
- device pci 14.3 on # CNVi wifi
+ device ref shared_sram on end
+ device ref cnvi_wifi on
chip drivers/wifi/generic
register "wake" = "PME_B0_EN_BIT"
device generic 0 on end
end
end
- device pci 14.5 off end # SDCard
- device pci 15.0 on # I2C #0
+ device ref i2c0 on
chip drivers/i2c/hid
register "generic.hid" = ""SYNA1202""
register "generic.desc" = ""Synaptics Touchpad""
@@ -113,45 +106,28 @@ chip soc/intel/cannonlake
device i2c 2c on end
end
end
- device pci 15.1 off end # I2C #1
- device pci 15.2 off end # I2C #2
- device pci 15.3 off end # I2C #3
- device pci 16.0 on end # Management Engine Interface 1
- device pci 16.1 off end # Management Engine Interface 2
- device pci 16.2 off end # Management Engine IDE-R
- device pci 16.3 off end # Management Engine KT Redirection
- device pci 16.4 off end # Management Engine Interface 3
- device pci 16.5 off end # Management Engine Interface 4
- device pci 17.0 on # SATA
+ device ref sata on
register "SataPortsEnable" = "{
[1] = 1, /* SATA1A (SSD) */
[3] = 1, /* SATA3 (M.2_SATA3) */
[4] = 1, /* SATA4 (SSD2) */
}"
end
- device pci 19.2 off end # UART #2
- device pci 1a.0 off end # eMMC
- device pci 1b.0 on # PCI Express Port 17
+ device ref pcie_rp17 on
# PCI Express root port #17 x4, Clock 14 (SSD2)
register "PcieRpEnable[16]" = "1"
register "PcieRpLtrEnable[16]" = "1"
register "PcieClkSrcUsage[14]" = "16"
register "PcieClkSrcClkReq[14]" = "14"
end
- device pci 1b.1 off end # PCI Express Port 18
- device pci 1b.2 off end # PCI Express Port 19
- device pci 1b.3 off end # PCI Express Port 20
- device pci 1b.4 on # PCI Express Port 21
+ device ref pcie_rp21 on
# PCI Express root port #21 x4, Clock 15 (SSD3)
register "PcieRpEnable[20]" = "1"
register "PcieRpLtrEnable[20]" = "1"
register "PcieClkSrcUsage[15]" = "20"
register "PcieClkSrcClkReq[15]" = "15"
end
- device pci 1b.5 off end # PCI Express Port 22
- device pci 1b.6 off end # PCI Express Port 23
- device pci 1b.7 off end # PCI Express Port 24
- device pci 1c.0 on # PCI Express Port 1
+ device ref pcie_rp1 on
# PCI Express root port #1 x4, Clock 6 (Thunderbolt)
register "PcieRpEnable[0]" = "1"
register "PcieRpLtrEnable[0]" = "1"
@@ -159,56 +135,42 @@ chip soc/intel/cannonlake
register "PcieClkSrcUsage[6]" = "PCIE_CLK_RP0" # 0 is converted to PCIE_CLK_NOTUSED
register "PcieClkSrcClkReq[6]" = "6"
end
- device pci 1c.1 off end # PCI Express Port 2
- device pci 1c.2 off end # PCI Express Port 3
- device pci 1c.3 off end # PCI Express Port 4
- device pci 1c.4 on # PCI Express Port 5
+ device ref pcie_rp5 on
# PCI Express root port #5 x4, Clock 10 (USB 3.2)
register "PcieRpEnable[4]" = "1"
register "PcieRpLtrEnable[4]" = "1"
register "PcieClkSrcUsage[10]" = "4"
register "PcieClkSrcClkReq[10]" = "10"
end
- device pci 1c.5 off end # PCI Express Port 6
- device pci 1c.6 off end # PCI Express Port 7
- device pci 1c.7 off end # PCI Express Port 8
- device pci 1d.0 on # PCI Express Port 9
+ device ref pcie_rp9 on
# PCI Express root port #9 x4, Clock 8 (SSD)
register "PcieRpEnable[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[8]" = "8"
register "PcieClkSrcClkReq[8]" = "8"
end
- device pci 1d.1 off end # PCI Express Port 10
- device pci 1d.2 off end # PCI Express Port 11
- device pci 1d.3 off end # PCI Express Port 12
- device pci 1d.4 on # PCI Express Port 13
+ device ref pcie_rp13 on
# PCI Express root port #13 x1, Clock 0 (WLAN)
register "PcieRpEnable[12]" = "1"
register "PcieRpLtrEnable[12]" = "1"
register "PcieClkSrcUsage[0]" = "12"
register "PcieClkSrcClkReq[0]" = "0"
end
- device pci 1d.5 on # PCI Express Port 14
+ device ref pcie_rp14 on
# PCI Express root port #14 x1, Clock 1 (GLAN)
register "PcieRpEnable[13]" = "1"
register "PcieRpLtrEnable[13]" = "1"
register "PcieClkSrcUsage[1]" = "13"
register "PcieClkSrcClkReq[1]" = "1"
end
- device pci 1d.6 on # PCI Express Port 15
+ device ref pcie_rp15 on
# PCI Express root port #15 x1, Clock 4 (Card Reader)
register "PcieRpEnable[14]" = "1"
register "PcieRpLtrEnable[14]" = "1"
register "PcieClkSrcUsage[4]" = "14"
register "PcieClkSrcClkReq[4]" = "4"
end
- device pci 1d.7 off end # PCI Express Port 16
- device pci 1e.0 off end # UART #0
- device pci 1e.1 off end # UART #1
- device pci 1e.2 off end # GSPI #0
- device pci 1e.3 off end # GSPI #1
- device pci 1f.0 on # LPC Interface
+ device ref lpc_espi on
register "gen1_dec" = "0x00040069"
register "gen2_dec" = "0x00fc0e01"
register "gen3_dec" = "0x00fc0f01"
@@ -216,13 +178,9 @@ chip soc/intel/cannonlake
device pnp 0c31.0 on end
end
end
- device pci 1f.1 off end # P2SB
- device pci 1f.2 hidden end # Power Management Controller
- device pci 1f.3 on # Intel HDA
+ device ref hda on
register "PchHdaAudioLinkHda" = "1"
end
- device pci 1f.4 on end # SMBus
- device pci 1f.5 on end # PCH SPI
- device pci 1f.6 off end # GbE
+ device ref smbus on end
end
end
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 04:01:47 +0000