diff options
| -rw-r--r-- | src/soc/intel/broadwell/Kconfig | 21 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/Makefile.inc | 8 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/bootblock/cpu.c | 63 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/bootblock/pch.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/bootblock/systemagent.c | 3 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/romstage/romstage.c | 4 |
7 files changed, 26 insertions, 78 deletions
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig index 83ccf7b9d8..9dd2f4f414 100644 --- a/src/soc/intel/broadwell/Kconfig +++ b/src/soc/intel/broadwell/Kconfig @@ -44,6 +44,8 @@ config CPU_SPECIFIC_OPTIONS select HAVE_POWER_STATE_AFTER_FAILURE select HAVE_POWER_STATE_PREVIOUS_AFTER_FAILURE select NO_FIXED_XIP_ROM_SIZE + select C_ENVIRONMENT_BOOTBLOCK + select NO_BOOTBLOCK_CONSOLE config PCIEXP_ASPM bool @@ -69,18 +71,6 @@ config VBOOT select VBOOT_MUST_REQUEST_DISPLAY select VBOOT_STARTS_IN_ROMSTAGE -config BOOTBLOCK_CPU_INIT - string - default "soc/intel/broadwell/bootblock/cpu.c" - -config BOOTBLOCK_NORTHBRIDGE_INIT - string - default "soc/intel/broadwell/bootblock/systemagent.c" - -config BOOTBLOCK_SOUTHBRIDGE_INIT - string - default "soc/intel/broadwell/bootblock/pch.c" - config MMCONF_BASE_ADDRESS hex default 0xf0000000 @@ -123,6 +113,13 @@ config DCACHE_RAM_MRC_VAR_SIZE help The amount of cache-as-ram region required by the reference code. +config DCACHE_BSP_STACK_SIZE + hex + default 0x2000 + help + The amount of anticipated stack usage in CAR by bootblock and + other stages. + config HAVE_MRC bool "Add a Memory Reference Code binary" help diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index 1caf67adf4..eab8b37ba2 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -9,6 +9,13 @@ subdirs-y += ../../../cpu/intel/microcode subdirs-y += ../../../cpu/intel/turbo subdirs-y += ../../../cpu/intel/common +bootblock-y += bootblock/cpu.c +bootblock-y += bootblock/pch.c +bootblock-y += bootblock/systemagent.c +bootblock-y += ../../../cpu/intel/car/bootblock.c +bootblock-y += ../../../cpu/intel/car/non-evict/cache_as_ram.S +bootblock-y += ../../../cpu/x86/early_reset.S + ramstage-y += acpi.c ramstage-y += adsp.c ramstage-y += chip.c @@ -58,6 +65,7 @@ ramstage-y += stage_cache.c romstage-y += stage_cache.c postcar-y += stage_cache.c ramstage-y += systemagent.c +bootblock-y += tsc_freq.c ramstage-y += tsc_freq.c romstage-y += tsc_freq.c smm-y += tsc_freq.c diff --git a/src/soc/intel/broadwell/bootblock/cpu.c b/src/soc/intel/broadwell/bootblock/cpu.c index 2f1ac51981..f3c35f3441 100644 --- a/src/soc/intel/broadwell/bootblock/cpu.c +++ b/src/soc/intel/broadwell/bootblock/cpu.c @@ -19,47 +19,10 @@ #include <cpu/x86/mtrr.h> #include <arch/io.h> #include <halt.h> -#include <cpu/intel/microcode/microcode.c> #include <soc/rcba.h> #include <soc/msr.h> - -static void set_var_mtrr(unsigned int reg, unsigned int base, unsigned int size, - unsigned int type) -{ - /* Bit Bit 32-35 of MTRRphysMask should be set to 1 */ - msr_t basem, maskm; - basem.lo = base | type; - basem.hi = 0; - wrmsr(MTRR_PHYS_BASE(reg), basem); - maskm.lo = ~(size - 1) | MTRR_PHYS_MASK_VALID; - maskm.hi = (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1; - wrmsr(MTRR_PHYS_MASK(reg), maskm); -} - -static void enable_rom_caching(void) -{ - msr_t msr; - - disable_cache(); - set_var_mtrr(1, CACHE_ROM_BASE, CACHE_ROM_SIZE, MTRR_TYPE_WRPROT); - enable_cache(); - - /* Enable Variable MTRRs */ - msr.hi = 0x00000000; - msr.lo = 0x00000800; - wrmsr(MTRR_DEF_TYPE_MSR, msr); -} - -static void bootblock_mdelay(int ms) -{ - u32 target = ms * 24 * 1000; - msr_t current; - msr_t start = rdmsr(MSR_COUNTER_24_MHZ); - - do { - current = rdmsr(MSR_COUNTER_24_MHZ); - } while ((current.lo - start.lo) < target); -} +#include <delay.h> +#include <cpu/intel/car/bootblock.h> static void set_flex_ratio_to_tdp_nominal(void) { @@ -102,7 +65,7 @@ static void set_flex_ratio_to_tdp_nominal(void) RCBA32_OR(SOFT_RESET_CTRL, 1); /* Delay before reset to avoid potential TPM lockout */ - bootblock_mdelay(30); + mdelay(30); /* Issue warm reset, will be "CPU only" due to soft reset data */ outb(0x0, 0xcf9); @@ -110,26 +73,8 @@ static void set_flex_ratio_to_tdp_nominal(void) halt(); } -static void check_for_clean_reset(void) -{ - msr_t msr; - msr = rdmsr(MTRR_DEF_TYPE_MSR); - - /* Use the MTRR default type MSR as a proxy for detecting INIT#. - * Reset the system if any known bits are set in that MSR. That is - * an indication of the CPU not being properly reset. */ - if (msr.lo & (MTRR_DEF_TYPE_EN | MTRR_DEF_TYPE_FIX_EN)) { - outb(0x0, 0xcf9); - outb(0x6, 0xcf9); - halt(); - } -} - -static void bootblock_cpu_init(void) +void bootblock_early_cpu_init(void) { /* Set flex ratio and reset if needed */ set_flex_ratio_to_tdp_nominal(); - check_for_clean_reset(); - enable_rom_caching(); - intel_update_microcode_from_cbfs(); } diff --git a/src/soc/intel/broadwell/bootblock/pch.c b/src/soc/intel/broadwell/bootblock/pch.c index dc7f42a625..1301610947 100644 --- a/src/soc/intel/broadwell/bootblock/pch.c +++ b/src/soc/intel/broadwell/bootblock/pch.c @@ -19,6 +19,7 @@ #include <soc/pci_devs.h> #include <soc/rcba.h> #include <soc/spi.h> +#include <cpu/intel/car/bootblock.h> /* * Enable Prefetching and Caching. @@ -66,7 +67,7 @@ static void set_spi_speed(void) SPIBAR8(SPIBAR_SSFC + 2) = ssfc; } -static void bootblock_southbridge_init(void) +void bootblock_early_southbridge_init(void) { map_rcba(); enable_spi_prefetch(); diff --git a/src/soc/intel/broadwell/bootblock/systemagent.c b/src/soc/intel/broadwell/bootblock/systemagent.c index e618636eb2..7aaed789ac 100644 --- a/src/soc/intel/broadwell/bootblock/systemagent.c +++ b/src/soc/intel/broadwell/bootblock/systemagent.c @@ -16,8 +16,9 @@ #include <device/pci_ops.h> #include <soc/pci_devs.h> #include <soc/systemagent.h> +#include <cpu/intel/car/bootblock.h> -static void bootblock_northbridge_init(void) +void bootblock_early_northbridge_init(void) { uint32_t reg; diff --git a/src/soc/intel/broadwell/romstage/Makefile.inc b/src/soc/intel/broadwell/romstage/Makefile.inc index cc0a05124f..ea17d67061 100644 --- a/src/soc/intel/broadwell/romstage/Makefile.inc +++ b/src/soc/intel/broadwell/romstage/Makefile.inc @@ -1,5 +1,3 @@ -cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S - romstage-y += ../../../../cpu/intel/car/romstage.c romstage-y += cpu.c romstage-y += pch.c diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 25c47c62c2..54434a3153 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -67,9 +67,7 @@ void platform_enter_postcar(void) /* Entry from cpu/intel/car/romstage.c. */ void mainboard_romstage_entry(unsigned long bist) { - struct romstage_params rp = { - .bist = bist, - }; + struct romstage_params rp = { 0 }; post_code(0x30); |