diff options
| -rw-r--r-- | src/mainboard/google/brya/variants/craask/fw_config.c | 49 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/craask/gpio.c | 12 | ||||
| -rw-r--r-- | src/mainboard/google/brya/variants/craask/overridetree.cb | 8 |
3 files changed, 69 insertions, 0 deletions
diff --git a/src/mainboard/google/brya/variants/craask/fw_config.c b/src/mainboard/google/brya/variants/craask/fw_config.c index 139f3eb820..d6679108f8 100644 --- a/src/mainboard/google/brya/variants/craask/fw_config.c +++ b/src/mainboard/google/brya/variants/craask/fw_config.c @@ -47,8 +47,42 @@ static const struct pad_config stylus_disable_pads[] = { PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), }; +static const struct pad_config nvme_disable_pads[] = { + /* B4 : SSD_PERST_L */ + PAD_NC_LOCK(GPP_B4, NONE, LOCK_CONFIG), + /* D11 : EN_PP3300_SSD */ + PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG), + /* E17 : SSD_PLN_L */ + PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG), + /* + * Note: don't disable GPP_D6 = SSD_CLKREQ_ODL, since this is used as + * WWAN_EN on LTE variants. + */ +}; + +/* + * GPP_D6 is used as WWAN_EN on LTE variants and SSD_CLKREQ_ODL on NVMe + * variants (there is no craask variant supporting both LTE and NVMe). + * In craask/gpio.c, it's set to WWAN_EN since this needs to be done in + * bootblock. So we override it to SSD_CLKREQ_ODL here for NVMe variants. + */ +static const struct pad_config nvme_enable_pads[] = { + /* D6 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */ + PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1), +}; + void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { + /* + * Since GPP_D6 is used as WWAN_EN on LTE variants and SSD_CLKREQ_ODL on + * NVMe variants, we don't support both together. If there's a variant + * using both in the future, this GPIO handling will need to be updated. + */ + if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE)) && + fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) { + printk(BIOS_ERR, "LTE and NVMe together is not supported on craask\n"); + } + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { printk(BIOS_INFO, "Disable LTE-related GPIO pins on craask.\n"); gpio_padbased_override(padbased_table, lte_disable_pads, @@ -72,4 +106,19 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) gpio_padbased_override(padbased_table, stylus_disable_pads, ARRAY_SIZE(stylus_disable_pads)); } + + if (!fw_config_is_provisioned() || + fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) { + /* + * Note: this must be done after lte_disable_pads, otherwise + * GPP_D6 will be disabled again. + */ + printk(BIOS_INFO, "Enable NVMe SSD GPIO pins.\n"); + gpio_padbased_override(padbased_table, nvme_enable_pads, + ARRAY_SIZE(nvme_enable_pads)); + } else { + printk(BIOS_INFO, "Disable NVMe SSD GPIO pins.\n"); + gpio_padbased_override(padbased_table, nvme_disable_pads, + ARRAY_SIZE(nvme_disable_pads)); + } } diff --git a/src/mainboard/google/brya/variants/craask/gpio.c b/src/mainboard/google/brya/variants/craask/gpio.c index 980b0bf358..5d0db35caa 100644 --- a/src/mainboard/google/brya/variants/craask/gpio.c +++ b/src/mainboard/google/brya/variants/craask/gpio.c @@ -9,10 +9,16 @@ static const struct pad_config override_gpio_table[] = { /* A8 : WWAN_RF_DISABLE_ODL */ PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), /* D6 : WWAN_EN */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* D7 : WLAN_CLKREQ_ODL */ PAD_NC(GPP_D7, NONE), + /* D11 : EN_PP3300_SSD */ + PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG), + /* E17 : SSD_PLN_L */ + PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG), /* F12 : WWAN_RST_L */ PAD_CFG_GPO_LOCK(GPP_F12, 1, LOCK_CONFIG), /* H3 : WLAN_PCIE_WAKE_ODL */ @@ -41,6 +47,8 @@ static const struct pad_config override_gpio_table[] = { /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 0, DEEP), /* F12 : GSXDOUT ==> WWAN_RST_L */ PAD_CFG_GPO(GPP_F12, 0, DEEP), /* H12 : UART0_RTS# ==> SD_PERST_L */ @@ -61,11 +69,15 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* D11 : EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_D11, 1, DEEP), /* H13 : UART0_CTS# ==> EN_PP3300_SD_X */ PAD_CFG_GPO(GPP_H13, 1, DEEP), }; static const struct pad_config romstage_gpio_table[] = { + /* B4 : SSD_PERST_L */ + PAD_CFG_GPO(GPP_B4, 1, DEEP), /* H12 : UART0_RTS# ==> SD_PERST_L */ PAD_CFG_GPO(GPP_H12, 1, DEEP), }; diff --git a/src/mainboard/google/brya/variants/craask/overridetree.cb b/src/mainboard/google/brya/variants/craask/overridetree.cb index 0687bf5cda..bf05d255d1 100644 --- a/src/mainboard/google/brya/variants/craask/overridetree.cb +++ b/src/mainboard/google/brya/variants/craask/overridetree.cb @@ -445,6 +445,14 @@ chip soc/intel/alderlake end probe SD_CARD SD_GL9750S end + device ref pcie_rp9 on + # Enable NVMe SSD PCIe 9-12 using clk 1 + register "pch_pcie_rp[PCH_RP(9)]" = "{ + .clk_src = 1, + .clk_req = 1, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + end device ref pch_espi on chip ec/google/chromeec use conn0 as mux_conn[0] |