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-rw-r--r--src/soc/intel/jasperlake/chip.h18
-rw-r--r--src/soc/intel/jasperlake/fsp_params.c4
2 files changed, 22 insertions, 0 deletions
diff --git a/src/soc/intel/jasperlake/chip.h b/src/soc/intel/jasperlake/chip.h
index f157f9218b..0ed42050e9 100644
--- a/src/soc/intel/jasperlake/chip.h
+++ b/src/soc/intel/jasperlake/chip.h
@@ -341,6 +341,24 @@ struct soc_intel_jasperlake_config {
* - PM_CFG.SLP_LAN_MIN_ASST_WDTH
*/
uint8_t PchPmPwrCycDur;
+
+ /*
+ * FIVR RFI Frequency
+ * PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100KHz.
+ * 0: Auto.
+ * Range varies based on XTAL clock:
+ * 0-1918 (Up to 191.8HMz) for 24MHz clock;
+ * 0-1535 (Up to 153.5MHz) for 19MHz clock.
+ */
+ uint16_t FivrRfiFrequency;
+
+ /*
+ * FIVR RFI Spread Spectrum
+ * Set the Spread Spectrum Range. <b>0: 0%</b>;
+ * FIVR RFI Spread Spectrum, in 0.1% increments.
+ * Range: 0.0% to 10.0% (0-100)
+ */
+ uint8_t FivrSpreadSpectrum;
};
typedef struct soc_intel_jasperlake_config config_t;
diff --git a/src/soc/intel/jasperlake/fsp_params.c b/src/soc/intel/jasperlake/fsp_params.c
index db27234067..92c35c62dc 100644
--- a/src/soc/intel/jasperlake/fsp_params.c
+++ b/src/soc/intel/jasperlake/fsp_params.c
@@ -216,6 +216,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
/* Provide correct UART number for FSP debug logs */
params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
+ /* Configure FIVR RFI related settings */
+ params->FivrRfiFrequency = config->FivrRfiFrequency;
+ params->FivrSpreadSpectrum = config->FivrSpreadSpectrum;
+
/* Apply minimum assertion width settings if non-zero */
if (config->PchPmSlpS3MinAssert)
params->PchPmSlpS3MinAssert = config->PchPmSlpS3MinAssert;