diff options
| -rw-r--r-- | src/soc/intel/common/block/gpio/Kconfig | 5 | ||||
| -rw-r--r-- | src/soc/intel/common/block/gpio/gpio.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/gpio_defs.h | 16 |
3 files changed, 25 insertions, 0 deletions
diff --git a/src/soc/intel/common/block/gpio/Kconfig b/src/soc/intel/common/block/gpio/Kconfig index c946545355..1c76c0a319 100644 --- a/src/soc/intel/common/block/gpio/Kconfig +++ b/src/soc/intel/common/block/gpio/Kconfig @@ -36,4 +36,9 @@ config SOC_INTEL_COMMON_BLOCK_GPIO_DUAL_ROUTE_SUPPORT bool default n +# Used to program VCCIO Selection as 1.8V or 3.3V +config SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_VCCIOSEL + bool + default n + endif diff --git a/src/soc/intel/common/block/gpio/gpio.c b/src/soc/intel/common/block/gpio/gpio.c index d4a312bf9a..5591805120 100644 --- a/src/soc/intel/common/block/gpio/gpio.c +++ b/src/soc/intel/common/block/gpio/gpio.c @@ -39,7 +39,11 @@ PAD_CFG1_IOSSTATE_MASK) #endif +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_VCCIOSEL) +#define PAD_DW2_MASK (PAD_CFG2_VCCIOSEL_MASK | PAD_CFG2_DEBOUNCE_MASK) +#else #define PAD_DW2_MASK (PAD_CFG2_DEBOUNCE_MASK) +#endif /* SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_VCCIOSEL */ #define PAD_DW3_MASK (0) #define MISCCFG_GPE0_DW0_SHIFT 8 diff --git a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h index d3249bcbbb..212a0c745b 100644 --- a/src/soc/intel/common/block/include/intelblocks/gpio_defs.h +++ b/src/soc/intel/common/block/include/intelblocks/gpio_defs.h @@ -123,6 +123,14 @@ #define PAD_CFG1_TOL_1V8 (0x1 << 25) #endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL */ +/* On SoCs with more than 2 PAD_CFG registers, some of them support programmable VCCIO. + 0(default)=3.3V, 1=1.8V */ +#if CONFIG(SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_VCCIOSEL) +#define PAD_CFG2_VCCIOSEL_MASK (0x1 << 8) +#define PAD_CFG2_VCCIOSEL_3V3 (0x0 << 8) +#define PAD_CFG2_VCCIOSEL_1V8 (0x1 << 8) +#endif /* CONFIG_SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_VCCIOSEL */ + #define PAD_FUNC(value) PAD_CFG0_MODE_##value #define PAD_RESET(value) PAD_CFG0_LOGICAL_RESET_##value #define PAD_RX_POL(value) PAD_CFG0_RX_POL_##value @@ -252,6 +260,14 @@ PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ PAD_PULL(pull) | PAD_IOSSTATE(iosstate) | PAD_IOSTERM(ioterm)) +/* General purpose output with VCCIO Select. */ +#define PAD_CFG_GPO_VCCIOSEL(pad, val, rst, vcciosel) \ + _PAD_CFG_STRUCT_3(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | \ + PAD_TRIG(OFF) | PAD_BUF(RX_DISABLE) | !!val, \ + PAD_PULL(NONE) | PAD_IOSSTATE(TxLASTRxE), \ + PAD_CFG2_VCCIOSEL_##vcciosel) + /* General purpose input */ #define PAD_CFG_GPI(pad, pull, rst) \ _PAD_CFG_STRUCT(pad, \ |