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-rw-r--r--src/soc/intel/tigerlake/acpi.c6
-rw-r--r--src/soc/intel/tigerlake/fsp_params.c25
-rw-r--r--src/soc/intel/tigerlake/romstage/fsp_params.c44
3 files changed, 22 insertions, 53 deletions
diff --git a/src/soc/intel/tigerlake/acpi.c b/src/soc/intel/tigerlake/acpi.c
index f245457376..e8d665c322 100644
--- a/src/soc/intel/tigerlake/acpi.c
+++ b/src/soc/intel/tigerlake/acpi.c
@@ -172,11 +172,10 @@ uint32_t soc_read_sci_irq_select(void)
static unsigned long soc_fill_dmar(unsigned long current)
{
- const struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
- if (is_dev_enabled(igfx_dev) && gfxvtbar && gfxvten) {
+ if (is_devfn_enabled(SA_DEVFN_IGD) && gfxvtbar && gfxvten) {
unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, gfxvtbar);
@@ -185,11 +184,10 @@ static unsigned long soc_fill_dmar(unsigned long current)
acpi_dmar_drhd_fixup(tmp, current);
}
- const struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU);
uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
- if (is_dev_enabled(ipu_dev) && ipuvtbar && ipuvten) {
+ if (is_devfn_enabled(SA_DEVFN_IPU) && ipuvtbar && ipuvten) {
unsigned long tmp = current;
current += acpi_create_dmar_drhd(current, 0, 0, ipuvtbar);
diff --git a/src/soc/intel/tigerlake/fsp_params.c b/src/soc/intel/tigerlake/fsp_params.c
index 220140bfd1..823f8e543c 100644
--- a/src/soc/intel/tigerlake/fsp_params.c
+++ b/src/soc/intel/tigerlake/fsp_params.c
@@ -107,8 +107,7 @@ static int get_disable_mask(struct soc_intel_tigerlake_config *config)
disable_mask |= LPM_S0i3_3 | LPM_S0i3_4 | LPM_S0i2_2;
/* If CNVi or ISH is used, S0i3.2/S0i3.3/S0i3.4 cannot be achieved. */
- if (is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI)) ||
- is_dev_enabled(pcidev_path_on_root(PCH_DEVFN_ISH)))
+ if (is_devfn_enabled(PCH_DEVFN_CNVI_WIFI) || is_devfn_enabled(PCH_DEVFN_ISH))
disable_mask |= LPM_S0i3_2 | LPM_S0i3_3 | LPM_S0i3_4;
return disable_mask;
@@ -156,8 +155,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->GraphicsConfigPtr = (uintptr_t)vbt_get();
/* Check if IGD is present and fill Graphics init param accordingly */
- dev = pcidev_path_on_root(SA_DEVFN_IGD);
- params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_dev_enabled(dev);
+ params->PeiGraphicsPeimInit = CONFIG(RUN_FSP_GOP) && is_devfn_enabled(SA_DEVFN_IGD);
/* Use coreboot MP PPI services if Kconfig is enabled */
if (CONFIG(USE_INTEL_FSP_TO_CALL_COREBOOT_PUBLISH_MP_PPI))
@@ -275,8 +273,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->SerialIoUartAutoFlow[CONFIG_UART_FOR_CONSOLE] = 0;
/* SATA */
- dev = pcidev_path_on_root(PCH_DEVFN_SATA);
- params->SataEnable = is_dev_enabled(dev);
+ params->SataEnable = is_devfn_enabled(PCH_DEVFN_SATA);
if (params->SataEnable) {
params->SataMode = config->SataMode;
params->SataSalpSupport = config->SataSalpSupport;
@@ -334,12 +331,10 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->TccActivationOffset = config->tcc_offset;
/* LAN */
- dev = pcidev_path_on_root(PCH_DEVFN_GBE);
- params->PchLanEnable = is_dev_enabled(dev);
+ params->PchLanEnable = is_devfn_enabled(PCH_DEVFN_GBE);
/* CNVi */
- dev = pcidev_path_on_root(PCH_DEVFN_CNVI_WIFI);
- params->CnviMode = is_dev_enabled(dev);
+ params->CnviMode = is_devfn_enabled(PCH_DEVFN_CNVI_WIFI);
params->CnviBtCore = config->CnviBtCore;
params->CnviBtAudioOffload = config->CnviBtAudioOffload;
/* Assert if CNVi BT is enabled without CNVi being enabled. */
@@ -348,15 +343,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
assert(params->CnviBtCore || !params->CnviBtAudioOffload);
/* VMD */
- dev = pcidev_path_on_root(SA_DEVFN_VMD);
- params->VmdEnable = is_dev_enabled(dev);
+ params->VmdEnable = is_devfn_enabled(SA_DEVFN_VMD);
/* THC */
- dev = pcidev_path_on_root(PCH_DEVFN_THC0);
- params->ThcPort0Assignment = is_dev_enabled(dev) ? THC_0 : THC_NONE;
-
- dev = pcidev_path_on_root(PCH_DEVFN_THC1);
- params->ThcPort1Assignment = is_dev_enabled(dev) ? THC_1 : THC_NONE;
+ params->ThcPort0Assignment = is_devfn_enabled(PCH_DEVFN_THC0) ? THC_0 : THC_NONE;
+ params->ThcPort1Assignment = is_devfn_enabled(PCH_DEVFN_THC1) ? THC_1 : THC_NONE;
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c
index 231bba7955..dca84cc725 100644
--- a/src/soc/intel/tigerlake/romstage/fsp_params.c
+++ b/src/soc/intel/tigerlake/romstage/fsp_params.c
@@ -20,13 +20,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
{
unsigned int i;
uint32_t cpu_id, mask = 0;
- const struct device *dev;
- dev = pcidev_path_on_root(SA_DEVFN_IGD);
- if (!CONFIG(SOC_INTEL_DISABLE_IGD) && is_dev_enabled(dev))
- m_cfg->InternalGfx = 1;
- else
- m_cfg->InternalGfx = 0;
+ m_cfg->InternalGfx = !CONFIG(SOC_INTEL_DISABLE_IGD) && is_devfn_enabled(SA_DEVFN_IGD);
/* If IGD is enabled, set IGD stolen size to 60MB. Otherwise, skip IGD init in FSP */
m_cfg->IgdDvmt50PreAlloc = m_cfg->InternalGfx ? 0xFE : 0;
@@ -74,8 +69,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
DEBUG_INTERFACE_UART_8250IO : DEBUG_INTERFACE_LPSS_SERIAL_IO;
/* TraceHub configuration */
- dev = pcidev_path_on_root(PCH_DEVFN_TRACEHUB);
- if (is_dev_enabled(dev) && config->TraceHubMode) {
+ if (is_devfn_enabled(PCH_DEVFN_TRACEHUB) && config->TraceHubMode) {
m_cfg->PcdDebugInterfaceFlags |= DEBUG_INTERFACE_TRACEHUB;
m_cfg->PchTraceHubMode = config->TraceHubMode;
m_cfg->CpuTraceHubMode = config->TraceHubMode;
@@ -85,8 +79,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->SerialIoUartDebugMode = PchSerialIoSkipInit;
/* ISH */
- dev = pcidev_path_on_root(PCH_DEVFN_ISH);
- m_cfg->PchIshEnable = is_dev_enabled(dev);
+ m_cfg->PchIshEnable = is_devfn_enabled(PCH_DEVFN_ISH);
/* Skip GPIO configuration from FSP */
m_cfg->GpioOverride = 0x1;
@@ -117,24 +110,14 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->TcssXdciEn = config->TcssXdciEn;
/* TCSS DMA */
- dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA0);
- m_cfg->TcssDma0En = is_dev_enabled(dev);
-
- dev = pcidev_path_on_root(SA_DEVFN_TCSS_DMA1);
- m_cfg->TcssDma1En = is_dev_enabled(dev);
+ m_cfg->TcssDma0En = is_devfn_enabled(SA_DEVFN_TCSS_DMA0);
+ m_cfg->TcssDma1En = is_devfn_enabled(SA_DEVFN_TCSS_DMA1);
/* USB4/TBT */
- dev = pcidev_path_on_root(SA_DEVFN_TBT0);
- m_cfg->TcssItbtPcie0En = is_dev_enabled(dev);
-
- dev = pcidev_path_on_root(SA_DEVFN_TBT1);
- m_cfg->TcssItbtPcie1En = is_dev_enabled(dev);
-
- dev = pcidev_path_on_root(SA_DEVFN_TBT2);
- m_cfg->TcssItbtPcie2En = is_dev_enabled(dev);
-
- dev = pcidev_path_on_root(SA_DEVFN_TBT3);
- m_cfg->TcssItbtPcie3En = is_dev_enabled(dev);
+ m_cfg->TcssItbtPcie0En = is_devfn_enabled(SA_DEVFN_TBT0);
+ m_cfg->TcssItbtPcie1En = is_devfn_enabled(SA_DEVFN_TBT1);
+ m_cfg->TcssItbtPcie2En = is_devfn_enabled(SA_DEVFN_TBT2);
+ m_cfg->TcssItbtPcie3En = is_devfn_enabled(SA_DEVFN_TBT3);
/* Hyper Threading */
m_cfg->HyperThreading = !config->HyperThreadingDisable;
@@ -149,8 +132,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->PlatformDebugConsent = CONFIG_SOC_INTEL_TIGERLAKE_DEBUG_CONSENT;
/* Audio: HDAUDIO_LINK_MODE I2S/SNDW */
- dev = pcidev_path_on_root(PCH_DEVFN_HDA);
- m_cfg->PchHdaEnable = is_dev_enabled(dev);
+ m_cfg->PchHdaEnable = is_devfn_enabled(PCH_DEVFN_HDA);
m_cfg->PchHdaDspEnable = config->PchHdaDspEnable;
m_cfg->PchHdaAudioLinkHdaEnable = config->PchHdaAudioLinkHdaEnable;
@@ -163,8 +145,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
sizeof(m_cfg->PchHdaAudioLinkSndwEnable));
/* IPU configuration */
- dev = pcidev_path_on_root(SA_DEVFN_IPU);
- m_cfg->SaIpuEnable = is_dev_enabled(dev);
+ m_cfg->SaIpuEnable = is_devfn_enabled(SA_DEVFN_IPU);
/* Vt-D config */
cpu_id = cpu_get_cpuid();
@@ -210,8 +191,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
m_cfg->SkipCpuReplacementCheck = !config->CpuReplacementCheck;
/* Skip CPU side PCIe enablement in FSP if device is disabled in devicetree */
- dev = pcidev_path_on_root(SA_DEVFN_CPU_PCIE);
- m_cfg->CpuPcieRpEnableMask = dev && dev->enabled;
+ m_cfg->CpuPcieRpEnableMask = is_devfn_enabled(SA_DEVFN_CPU_PCIE);
/* Change TmeEnable UPD value according to INTEL_TME Kconfig */
m_cfg->TmeEnable = CONFIG(INTEL_TME);
generated by cgit v1.2.3 (git 2.25.1) at 2024-11-11 11:46:31 +0000