diff options
| -rw-r--r-- | src/soc/intel/apollolake/romstage.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/cannonlake/romstage/fsp_params.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/cpu/cpulib.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/common/block/include/intelblocks/cpulib.h | 4 | ||||
| -rw-r--r-- | src/soc/intel/icelake/romstage/fsp_params.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/skylake/romstage/romstage.c | 2 | ||||
| -rw-r--r-- | src/soc/intel/tigerlake/romstage/fsp_params.c | 2 |
7 files changed, 8 insertions, 8 deletions
diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 141fae003a..0aa6c397e3 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -235,7 +235,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd) /* Only for GLK */ FSP_M_CONFIG *m_cfg = &mupd->FspmConfig; - m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->PrmrrSize = get_valid_prmrr_size(); /* * CpuMemoryTest in FSP tests 0 to 1M of the RAM after MRC init. diff --git a/src/soc/intel/cannonlake/romstage/fsp_params.c b/src/soc/intel/cannonlake/romstage/fsp_params.c index ac42e0054a..3cd148bc0f 100644 --- a/src/soc/intel/cannonlake/romstage/fsp_params.c +++ b/src/soc/intel/cannonlake/romstage/fsp_params.c @@ -52,7 +52,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd, const config_t *config) mask |= (1 << i); } m_cfg->PcieRpEnableMask = mask; - m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; #if CONFIG(SOC_INTEL_COMETLAKE) m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; diff --git a/src/soc/intel/common/block/cpu/cpulib.c b/src/soc/intel/common/block/cpu/cpulib.c index 9ff7923664..cbf9b1b9dd 100644 --- a/src/soc/intel/common/block/cpu/cpulib.c +++ b/src/soc/intel/common/block/cpu/cpulib.c @@ -340,7 +340,7 @@ void cpu_lt_lock_memory(void *unused) msr_set_bit(MSR_LT_CONTROL, LT_CONTROL_LOCK_BIT); } -int get_prmrr_size(void) +int get_valid_prmrr_size(void) { msr_t msr; int i; diff --git a/src/soc/intel/common/block/include/intelblocks/cpulib.h b/src/soc/intel/common/block/include/intelblocks/cpulib.h index 09f5e45577..d2b00efb2f 100644 --- a/src/soc/intel/common/block/include/intelblocks/cpulib.h +++ b/src/soc/intel/common/block/include/intelblocks/cpulib.h @@ -153,7 +153,7 @@ void mca_configure(void); /* Lock chipset memory registers to protect SMM */ void cpu_lt_lock_memory(void *unused); -/* Get the a supported PRMRR size in bytes with respect users choice */ -int get_prmrr_size(void); +/* Get a supported PRMRR size in bytes with respect to users choice */ +int get_valid_prmrr_size(void); #endif /* SOC_INTEL_COMMON_BLOCK_CPULIB_H */ diff --git a/src/soc/intel/icelake/romstage/fsp_params.c b/src/soc/intel/icelake/romstage/fsp_params.c index e944c76985..0801da23bf 100644 --- a/src/soc/intel/icelake/romstage/fsp_params.c +++ b/src/soc/intel/icelake/romstage/fsp_params.c @@ -45,7 +45,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, mask |= (1 << i); } m_cfg->PcieRpEnableMask = mask; - m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; diff --git a/src/soc/intel/skylake/romstage/romstage.c b/src/soc/intel/skylake/romstage/romstage.c index cefe7426e4..5e0d6871e2 100644 --- a/src/soc/intel/skylake/romstage/romstage.c +++ b/src/soc/intel/skylake/romstage/romstage.c @@ -220,7 +220,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, m_cfg->CmdTriStateDis = config->CmdTriStateDis; m_cfg->DdrFreqLimit = config->DdrFreqLimit; m_cfg->VmxEnable = CONFIG(ENABLE_VMX); - m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->PrmrrSize = get_valid_prmrr_size(); for (i = 0; i < ARRAY_SIZE(config->PcieRpEnable); i++) { if (config->PcieRpEnable[i]) mask |= (1<<i); diff --git a/src/soc/intel/tigerlake/romstage/fsp_params.c b/src/soc/intel/tigerlake/romstage/fsp_params.c index 4b68cb68c5..39572997c3 100644 --- a/src/soc/intel/tigerlake/romstage/fsp_params.c +++ b/src/soc/intel/tigerlake/romstage/fsp_params.c @@ -63,7 +63,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, memcpy(m_cfg->PcieClkSrcClkReq, config->PcieClkSrcClkReq, sizeof(config->PcieClkSrcClkReq)); - m_cfg->PrmrrSize = get_prmrr_size(); + m_cfg->PrmrrSize = get_valid_prmrr_size(); m_cfg->EnableC6Dram = config->enable_c6dram; /* Disable BIOS Guard */ m_cfg->BiosGuard = 0; |