diff options
| -rw-r--r-- | src/mainboard/amd/majolica/mainboard.c | 104 |
1 files changed, 104 insertions, 0 deletions
diff --git a/src/mainboard/amd/majolica/mainboard.c b/src/mainboard/amd/majolica/mainboard.c new file mode 100644 index 0000000000..0ba103e10d --- /dev/null +++ b/src/mainboard/amd/majolica/mainboard.c @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <amdblocks/amd_pci_util.h> +#include <commonlib/helpers.h> +#include <console/console.h> +#include <device/device.h> +#include <soc/acpi.h> +#include <string.h> +#include <types.h> + +/* + * These arrays set up the FCH PCI_INTR registers 0xC00/0xC01. + * This table is responsible for physically routing the PIC and + * IOAPIC IRQs to the different PCI devices on the system. It + * is read and written via registers 0xC00/0xC01 as an + * Index/Data pair. These values are chipset and mainboard + * dependent and should be updated accordingly. + */ +static uint8_t fch_pic_routing[0x80]; +static uint8_t fch_apic_routing[0x80]; + +_Static_assert(sizeof(fch_pic_routing) == sizeof(fch_apic_routing), + "PIC and APIC FCH interrupt tables must be the same size"); + +/* + * This controls the device -> IRQ routing. + * + * Hardcoded IRQs: + * 0: timer < soc/amd/common/acpi/lpc.asl + * 1: i8042 - Keyboard + * 2: cascade + * 8: rtc0 <- soc/amd/common/acpi/lpc.asl + * 9: acpi <- soc/amd/common/acpi/lpc.asl + */ +static const struct fch_irq_routing { + uint8_t intr_index; + uint8_t pic_irq_num; + uint8_t apic_irq_num; +} majolica_fch[] = { + { PIRQ_A, PIRQ_NC, PIRQ_NC }, + { PIRQ_B, PIRQ_NC, PIRQ_NC }, + { PIRQ_C, PIRQ_NC, PIRQ_NC }, + { PIRQ_D, PIRQ_NC, PIRQ_NC }, + { PIRQ_E, PIRQ_NC, PIRQ_NC }, + { PIRQ_F, PIRQ_NC, PIRQ_NC }, + { PIRQ_G, PIRQ_NC, PIRQ_NC }, + { PIRQ_H, PIRQ_NC, PIRQ_NC }, + + { PIRQ_SCI, PIRQ_NC, PIRQ_NC }, + { PIRQ_SD, PIRQ_NC, PIRQ_NC }, + { PIRQ_SDIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_SATA, PIRQ_NC, PIRQ_NC }, + { PIRQ_EMMC, PIRQ_NC, PIRQ_NC }, + { PIRQ_GPIO, PIRQ_NC, PIRQ_NC }, + { PIRQ_I2C2, PIRQ_NC, PIRQ_NC }, + { PIRQ_I2C3, PIRQ_NC, PIRQ_NC }, + { PIRQ_UART0, 4, 4 }, + { PIRQ_UART1, 3, 3 }, + + /* The MISC registers are not interrupt numbers */ + { PIRQ_MISC, 0xfa, 0x00 }, + { PIRQ_MISC0, 0x91, 0x00 }, + { PIRQ_HPET_L, 0x00, 0x00 }, + { PIRQ_HPET_H, 0x00, 0x00 }, +}; + +static void init_tables(void) +{ + const struct fch_irq_routing *entry; + int i; + + memset(fch_pic_routing, PIRQ_NC, sizeof(fch_pic_routing)); + memset(fch_apic_routing, PIRQ_NC, sizeof(fch_apic_routing)); + + for (i = 0; i < ARRAY_SIZE(majolica_fch); i++) { + entry = majolica_fch + i; + fch_pic_routing[entry->intr_index] = entry->pic_irq_num; + fch_apic_routing[entry->intr_index] = entry->apic_irq_num; + } +} + +static void pirq_setup(void) +{ + init_tables(); + intr_data_ptr = fch_apic_routing; + picr_data_ptr = fch_pic_routing; +} + +static void mainboard_init(void *chip_info) +{ +} + +static void majolica_enable(struct device *dev) +{ + printk(BIOS_INFO, "Mainboard " CONFIG_MAINBOARD_PART_NUMBER " Enable.\n"); + + /* Initialize the PIRQ data structures for consumption */ + pirq_setup(); +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, + .enable_dev = majolica_enable, +}; |