diff options
| -rw-r--r-- | src/soc/intel/broadwell/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/cpu.c | 26 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/cpu_info.c | 52 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/pcie.c | 1 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/sata.c | 4 | ||||
| -rw-r--r-- | src/soc/intel/broadwell/xhci.c | 10 |
6 files changed, 69 insertions, 26 deletions
diff --git a/src/soc/intel/broadwell/Makefile.inc b/src/soc/intel/broadwell/Makefile.inc index feead00f07..293918dcdb 100644 --- a/src/soc/intel/broadwell/Makefile.inc +++ b/src/soc/intel/broadwell/Makefile.inc @@ -13,6 +13,8 @@ ramstage-y += acpi.c ramstage-y += adsp.c ramstage-y += chip.c ramstage-y += cpu.c +ramstage-y += cpu_info.c +smm-y += cpu_info.c ramstage-$(CONFIG_ELOG) += elog.c ramstage-y += finalize.c ramstage-y += gpio.c diff --git a/src/soc/intel/broadwell/cpu.c b/src/soc/intel/broadwell/cpu.c index 8e05998c19..1f2ee0d7ba 100644 --- a/src/soc/intel/broadwell/cpu.c +++ b/src/soc/intel/broadwell/cpu.c @@ -103,32 +103,6 @@ static const u8 power_limit_time_msr_to_sec[] = { [0x11] = 128, }; -u32 cpu_family_model(void) -{ - return cpuid_eax(1) & 0x0fff0ff0; -} - -u32 cpu_stepping(void) -{ - return cpuid_eax(1) & 0xf; -} - -/* Dynamically determine if the part is ULT. */ -int cpu_is_ult(void) -{ - static int ult = -1; - - if (ult < 0) { - u32 fm = cpu_family_model(); - if (fm == BROADWELL_FAMILY_ULT || fm == HASWELL_FAMILY_ULT) - ult = 1; - else - ult = 0; - } - - return ult; -} - /* The core 100MHz BLCK is disabled in deeper c-states. One needs to calibrate * the 100MHz BCLCK against the 24MHz BLCK to restore the clocks properly * when a core is woken up. */ diff --git a/src/soc/intel/broadwell/cpu_info.c b/src/soc/intel/broadwell/cpu_info.c new file mode 100644 index 0000000000..a13ca94d42 --- /dev/null +++ b/src/soc/intel/broadwell/cpu_info.c @@ -0,0 +1,52 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA + */ + +#include <console/console.h> +#include <cpu/cpu.h> +#include <cpu/x86/msr.h> +#include <broadwell/cpu.h> +#include <broadwell/msr.h> +#include <broadwell/systemagent.h> + +u32 cpu_family_model(void) +{ + return cpuid_eax(1) & 0x0fff0ff0; +} + +u32 cpu_stepping(void) +{ + return cpuid_eax(1) & 0xf; +} + +/* Dynamically determine if the part is ULT. */ +int cpu_is_ult(void) +{ + static int ult = -1; + + if (ult < 0) { + u32 fm = cpu_family_model(); + if (fm == BROADWELL_FAMILY_ULT || fm == HASWELL_FAMILY_ULT) + ult = 1; + else + ult = 0; + } + + return ult; +} diff --git a/src/soc/intel/broadwell/pcie.c b/src/soc/intel/broadwell/pcie.c index bd5dc3c7a3..bd1c55a372 100644 --- a/src/soc/intel/broadwell/pcie.c +++ b/src/soc/intel/broadwell/pcie.c @@ -144,6 +144,7 @@ static void root_port_init_config(device_t dev) break; } + pcie_update_cfg(dev, 0x418, 0, 0x02000430); /* Cache pci device. */ rpc.ports[rp - 1] = dev; } diff --git a/src/soc/intel/broadwell/sata.c b/src/soc/intel/broadwell/sata.c index 0e2516185a..6859ffce37 100644 --- a/src/soc/intel/broadwell/sata.c +++ b/src/soc/intel/broadwell/sata.c @@ -209,6 +209,10 @@ static void sata_init(struct device *dev) reg32 |= (1 << 31) | (1 << 30) | (1 << 29); pci_write_config32(dev, 0x300, reg32); + reg32 = pci_read_config32(dev, 0x98); + reg32 |= 1 << 29; + pci_write_config32(dev, 0x98, reg32); + /* Register Lock */ reg32 = pci_read_config32(dev, 0x9c); reg32 |= (1 << 31); diff --git a/src/soc/intel/broadwell/xhci.c b/src/soc/intel/broadwell/xhci.c index 60223c1310..b330338169 100644 --- a/src/soc/intel/broadwell/xhci.c +++ b/src/soc/intel/broadwell/xhci.c @@ -25,6 +25,7 @@ #include <arch/io.h> #include <broadwell/ramstage.h> #include <broadwell/xhci.h> +#include <broadwell/cpu.h> #ifdef __SMM__ static u8 *usb_xhci_mem_base(device_t dev) @@ -147,6 +148,7 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) u16 reg16; u32 reg32; u8 *mem_base = usb_xhci_mem_base(dev); + u8 is_broadwell = !!(cpu_family_model() == BROADWELL_FAMILY_ULT); if (!mem_base || slp_typ < 3) return; @@ -157,6 +159,9 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) reg16 |= XHCI_PWR_CTL_SET_D0; pci_write_config16(dev, XHCI_PWR_CTL_STS, reg16); + if (!is_broadwell) { + /* This WA is only for lpt */ + /* Clear PCI 0xB0[14:13] */ reg32 = pci_read_config32(dev, 0xb0); reg32 &= ~((1 << 14) | (1 << 13)); @@ -174,6 +179,11 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ) reg32 = read32(mem_base + 0x80e0); reg32 |= (1 << 15); write32(mem_base + 0x80e0, reg32); + } + + reg32 = read32(mem_base + 0x8154); + reg32 &= ~(1 << 31); + write32(mem_base + 0x8154, reg32); /* Set D3Hot state and enable PME */ pci_or_config16(dev, XHCI_PWR_CTL_STS, XHCI_PWR_CTL_SET_D3); |