diff options
| -rw-r--r-- | src/mainboard/lenovo/x200/romstage.c | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/lenovo/x200/romstage.c b/src/mainboard/lenovo/x200/romstage.c index d8ed0391e1..71de5504db 100644 --- a/src/mainboard/lenovo/x200/romstage.c +++ b/src/mainboard/lenovo/x200/romstage.c @@ -89,16 +89,16 @@ void mainboard_romstage_entry(unsigned long bist) /* Check for S3 resume. */ const u32 pm1_cnt = inl(DEFAULT_PMBASE + 0x04); if (((pm1_cnt >> 10) & 7) == 5) { -#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) - printk(BIOS_DEBUG, "Resume from S3 detected.\n"); - s3resume = 1; - /* Clear SLP_TYPE. This will break stage2 but - * we care for that when we get there. - */ - outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04); -#else - printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); -#endif + if (acpi_s3_resume_allowed()) { + printk(BIOS_DEBUG, "Resume from S3 detected.\n"); + s3resume = 1; + /* Clear SLP_TYPE. This will break stage2 but + * we care for that when we get there. + */ + outl(pm1_cnt & ~(7 << 10), DEFAULT_PMBASE + 0x04); + } else { + printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n"); + } } /* RAM initialization */ |