diff options
| -rw-r--r-- | src/device/dram/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/device/dram/ddr2.c | 2 | ||||
| -rw-r--r-- | src/device/dram/ddr3.c | 23 | ||||
| -rw-r--r-- | src/device/dram/ddr4.c | 248 | ||||
| -rw-r--r-- | src/device/dram/ddr_common.c | 43 | ||||
| -rw-r--r-- | src/include/device/dram/common.h | 2 | ||||
| -rw-r--r-- | src/include/device/dram/ddr4.h | 87 |
7 files changed, 384 insertions, 23 deletions
diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index c982ef49e8..f397a534f2 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1 @@ -romstage-y += ddr3.c ddr2.c +romstage-y += ddr4.c ddr3.c ddr2.c ddr_common.c diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index 60588b880b..d66b576623 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -93,7 +93,7 @@ u16 spd_ddr2_calc_unique_crc(const u8 *spd, int len) for (i = 93; i <= 98; i++) id_bytes[j++] = spd[i]; - return ddr3_crc16(id_bytes, 15); + return ddr_crc16(id_bytes, 15); } /** diff --git a/src/device/dram/ddr3.c b/src/device/dram/ddr3.c index 834dc83db6..4a900fab47 100644 --- a/src/device/dram/ddr3.c +++ b/src/device/dram/ddr3.c @@ -23,6 +23,7 @@ #include <console/console.h> #include <device/device.h> #include <device/dram/ddr3.h> +#include <device/dram/common.h> #include <string.h> #include <memory_info.h> #include <cbmem.h> @@ -50,24 +51,6 @@ int spd_dimm_is_registered_ddr3(enum spd_dimm_type type) return 0; } -u16 ddr3_crc16(const u8 *ptr, int n_crc) -{ - int i; - u16 crc = 0; - - while (--n_crc >= 0) { - crc = crc ^ ((int)*ptr++ << 8); - for (i = 0; i < 8; ++i) - if (crc & 0x8000) { - crc = (crc << 1) ^ 0x1021; - } else { - crc = crc << 1; - } - } - - return crc; -} - /** * \brief Calculate the CRC of a DDR3 SPD * @@ -91,7 +74,7 @@ u16 spd_ddr3_calc_crc(u8 *spd, int len) /* Not enough bytes available to get the CRC */ return 0; - return ddr3_crc16(spd, n_crc); + return ddr_crc16(spd, n_crc); } /** @@ -108,7 +91,7 @@ u16 spd_ddr3_calc_unique_crc(u8 *spd, int len) /* Not enough bytes available to get the CRC */ return 0; - return ddr3_crc16(&spd[117], 11); + return ddr_crc16(&spd[117], 11); } /** diff --git a/src/device/dram/ddr4.c b/src/device/dram/ddr4.c new file mode 100644 index 0000000000..5927b41281 --- /dev/null +++ b/src/device/dram/ddr4.c @@ -0,0 +1,248 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <cbmem.h> +#include <device/device.h> +#include <device/dram/ddr4.h> +#include <string.h> +#include <memory_info.h> +#include <smbios.h> +#include <types.h> + +typedef enum { + BLOCK_0, /* Base Configuration and DRAM Parameters */ + BLOCK_1, + BLOCK_1_L, /* Standard Module Parameters */ + BLOCK_1_H, /* Hybrid Module Parameters */ + BLOCK_2, + BLOCK_2_L, /* Hybrid Module Extended Function Parameters */ + BLOCK_2_H, /* Manufacturing Information */ + BLOCK_3 /* End user programmable */ +} spd_block_type; + +typedef struct { + spd_block_type type; + uint16_t start; /* starting offset from beginning of the spd */ + uint16_t len; /* size of the block */ + uint16_t crc_start; /* offset from start of crc bytes, 0 if none */ +} spd_block; + +/* 'SPD contents architecture' as per datasheet */ +const spd_block spd_blocks[] = { + {.type = BLOCK_0, 0, 128, 126}, {.type = BLOCK_1, 128, 128, 126}, + {.type = BLOCK_1_L, 128, 64, 0}, {.type = BLOCK_1_H, 192, 64, 0}, + {.type = BLOCK_2_L, 256, 64, 62}, {.type = BLOCK_2_H, 320, 64, 0}, + {.type = BLOCK_3, 384, 128, 0} }; + +static bool verify_block(const spd_block *block, spd_raw_data spd) +{ + uint16_t crc, spd_crc; + + spd_crc = (spd[block->start + block->crc_start + 1] << 8) + | spd[block->start + block->crc_start]; + crc = ddr_crc16(&spd[block->start], block->len - 2); + + return spd_crc == crc; +} + +/* Check if given block is 'reserved' for a given module type */ +static bool block_exists(spd_block_type type, u8 dimm_type) +{ + bool is_hybrid; + + switch (type) { + case BLOCK_0: /* fall-through */ + case BLOCK_1: /* fall-through */ + case BLOCK_1_L: /* fall-through */ + case BLOCK_1_H: /* fall-through */ + case BLOCK_2_H: /* fall-through */ + case BLOCK_3: /* fall-through */ + return true; + case BLOCK_2_L: + is_hybrid = (dimm_type >> 4) & ((1 << 3) - 1); + if (is_hybrid) + return true; + return false; + default: /* fall-through */ + return false; + } +} + + +/** + * \brief Decode the raw SPD data + * + * Decodes a raw SPD data from a DDR4 DIMM, and organizes it into a + * @ref dimm_attr structure. The SPD data must first be read in a contiguous + * array, and passed to this function. + * + * @param dimm pointer to @ref dimm_attr structure where the decoded data is to + * be stored + * @param spd array of raw data previously read from the SPD. + * + * @return @ref spd_status enumerator + * SPD_STATUS_OK -- decoding was successful + * SPD_STATUS_INVALID -- invalid SPD or not a DDR4 SPD + * SPD_STATUS_CRC_ERROR -- checksum mismatch + */ +int spd_decode_ddr4(dimm_attr *dimm, spd_raw_data spd) +{ + u8 reg8; + u8 bus_width, sdram_width; + u16 cap_per_die_mbit; + u16 spd_bytes_total, spd_bytes_used; + const uint16_t spd_bytes_used_table[] = {0, 128, 256, 384, 512}; + + /* Make sure that the SPD dump is indeed from a DDR4 module */ + if (spd[2] != SPD_MEMORY_TYPE_DDR4_SDRAM) { + printk(BIOS_ERR, "Not a DDR4 SPD!\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + + spd_bytes_total = (spd[0] >> 4) & ((1 << 3) - 1); + spd_bytes_used = spd[0] & ((1 << 4) - 1); + + if (!spd_bytes_total || !spd_bytes_used) { + printk(BIOS_ERR, "SPD failed basic sanity checks\n"); + return SPD_STATUS_INVALID; + } + + spd_bytes_total = 256 << (spd_bytes_total - 1); + spd_bytes_used = spd_bytes_used_table[spd_bytes_used]; + + /* Verify CRC of blocks that have them, do not step over 'used' length */ + for (int i = 0; i < ARRAY_SIZE(spd_blocks); i++) { + /* this block is not checksumed */ + if (spd_blocks[i].crc_start == 0) + continue; + /* we shouldn't have this block */ + if (spd_blocks[i].start + spd_blocks[i].len > spd_bytes_used) + continue; + /* check if block exists in the current schema */ + if (!block_exists(spd_blocks[i].type, spd[3])) + continue; + if (!verify_block(&spd_blocks[i], spd)) { + printk(BIOS_ERR, "CRC failed for block %d\n", i); + return SPD_STATUS_CRC_ERROR; + } + } + + dimm->dram_type = SPD_MEMORY_TYPE_DDR4_SDRAM; + dimm->dimm_type = spd[3] & ((1 << 4) - 1); + + reg8 = spd[13] & ((1 << 4) - 1); + dimm->bus_width = reg8; + bus_width = 8 << (reg8 & ((1 << 3) - 1)); + + reg8 = spd[12] & ((1 << 3) - 1); + dimm->sdram_width = reg8; + sdram_width = 4 << reg8; + + reg8 = spd[4] & ((1 << 4) - 1); + dimm->cap_per_die_mbit = reg8; + cap_per_die_mbit = (1 << reg8) * 256; + + reg8 = (spd[12] >> 3) & ((1 << 3) - 1); + dimm->ranks = reg8 + 1; + + if (!bus_width || !sdram_width) { + printk(BIOS_ERR, "SPD information is invalid"); + dimm->size_mb = 0; + return SPD_STATUS_INVALID; + } + + /* seems to be only one, in mV */ + dimm->vdd_voltage = 1200; + + /* calculate size */ + dimm->size_mb = cap_per_die_mbit / 8 * bus_width / sdram_width * dimm->ranks; + + /* make sure we have the manufacturing information block */ + if (spd_bytes_used > 320) { + dimm->manufacturer_id = (spd[351] << 8) | spd[350]; + memcpy(dimm->part_number, &spd[329], SPD_DDR4_PART_LEN); + dimm->part_number[SPD_DDR4_PART_LEN] = 0; + memcpy(dimm->serial_number, &spd[325], sizeof(dimm->serial_number)); + } + return SPD_STATUS_OK; +} + +enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, const u16 selected_freq, + const dimm_attr *info) +{ + struct memory_info *mem_info; + struct dimm_info *dimm; + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_find(CBMEM_ID_MEMINFO); + if (!mem_info) { + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + + printk(BIOS_DEBUG, "CBMEM entry for DIMM info: 0x%p\n", mem_info); + if (!mem_info) + return CB_ERR; + + memset(mem_info, 0, sizeof(*mem_info)); + } + + if (mem_info->dimm_cnt >= ARRAY_SIZE(mem_info->dimm)) { + printk(BIOS_WARNING, "BUG: Too many DIMM infos for %s.\n", __func__); + return CB_ERR; + } + + dimm = &mem_info->dimm[mem_info->dimm_cnt]; + if (info->size_mb) { + dimm->ddr_type = MEMORY_TYPE_DDR4; + dimm->ddr_frequency = selected_freq; + dimm->dimm_size = info->size_mb; + dimm->channel_num = channel; + dimm->rank_per_dimm = info->ranks; + dimm->dimm_num = slot; + memcpy(dimm->module_part_number, info->part_number, SPD_DDR4_PART_LEN); + dimm->mod_id = info->manufacturer_id; + + switch (info->dimm_type) { + case SPD_DIMM_TYPE_SO_DIMM: + dimm->mod_type = SPD_SODIMM; + break; + case SPD_DIMM_TYPE_72B_SO_RDIMM: + dimm->mod_type = SPD_72B_SO_RDIMM; + break; + case SPD_DIMM_TYPE_UDIMM: + dimm->mod_type = SPD_UDIMM; + break; + case SPD_DIMM_TYPE_RDIMM: + dimm->mod_type = SPD_RDIMM; + break; + default: + dimm->mod_type = SPD_UNDEFINED; + break; + } + + dimm->bus_width = info->bus_width; + memcpy(dimm->serial, info->serial_number, + MIN(sizeof(dimm->serial), sizeof(info->serial_number))); + + dimm->vdd_voltage = info->vdd_voltage; + mem_info->dimm_cnt++; + } + + return CB_SUCCESS; +} diff --git a/src/device/dram/ddr_common.c b/src/device/dram/ddr_common.c new file mode 100644 index 0000000000..eb36bf52a0 --- /dev/null +++ b/src/device/dram/ddr_common.c @@ -0,0 +1,43 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/dram/common.h> +#include <types.h> + +/** + * \brief Calculate the CRC of a DDR SPD data + * + * @param spd pointer to raw SPD data + * @param len length of data in SPD + * + * @return the CRC of the SPD data + */ +u16 ddr_crc16(const u8 *ptr, int n_crc) +{ + int i; + u16 crc = 0; + + while (--n_crc >= 0) { + crc = crc ^ ((int)*ptr++ << 8); + for (i = 0; i < 8; ++i) + if (crc & 0x8000) + crc = (crc << 1) ^ 0x1021; + else + crc = crc << 1; + } + + return crc; +} diff --git a/src/include/device/dram/common.h b/src/include/device/dram/common.h index b1677c8a07..4c6f02eb00 100644 --- a/src/include/device/dram/common.h +++ b/src/include/device/dram/common.h @@ -67,6 +67,6 @@ enum spd_status { SPD_STATUS_INVALID_FIELD, }; -u16 ddr3_crc16(const u8 *ptr, int n_crc); +u16 ddr_crc16(const u8 *ptr, int n_crc); #endif /* DEVICE_DRAM_COMMON_H */ diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h new file mode 100644 index 0000000000..faa32995f8 --- /dev/null +++ b/src/include/device/dram/ddr4.h @@ -0,0 +1,87 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2019 Facebook, Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * JEDEC Standard No. 21-C + * Annex L: Serial Presence Detect (SPD) for DDR4 SDRAM Modules + */ + +#ifndef DEVICE_DRAM_DDR4L_H +#define DEVICE_DRAM_DDR4L_H + +/** + * @file ddr4.h + * + * \brief Utilities for decoding DDR4 SPDs + */ + +#include <stdint.h> +#include <spd.h> +#include <device/dram/common.h> +#include <types.h> + +#define SPD_DDR4_PART_OFF 329 +#define SPD_DDR4_PART_LEN 20 + + +/* + * Module type (byte 3, bits 3:0) of SPD + * This definition is specific to DDR4. DDR2/3 SPDs have a different structure. + */ +enum spd_dimm_type { + SPD_DIMM_TYPE_EXTENDED = 0x0, + SPD_DIMM_TYPE_RDIMM = 0x1, + SPD_DIMM_TYPE_UDIMM = 0x2, + SPD_DIMM_TYPE_SO_DIMM = 0x3, + SPD_DIMM_TYPE_LRDIMM = 0x4, + SPD_DIMM_TYPE_MINI_RDIMM = 0x5, + SPD_DIMM_TYPE_MINI_UDIMM = 0x6, + SPD_DIMM_TYPE_72B_SO_RDIMM = 0x8, + SPD_DIMM_TYPE_72B_SO_UDIMM = 0x9, + SPD_DIMM_TYPE_16B_SO_DIMM = 0xc, + SPD_DIMM_TYPE_32B_SO_DIMM = 0xd, + /* Masks to bits 3:0 to give the dimm type */ + SPD_DIMM_TYPE_MASK = 0xf +}; + +/** + * \brief DIMM characteristics + * + * The characteristics of each DIMM, as presented by the SPD + */ +typedef struct dimm_attr_st { + enum spd_memory_type dram_type; + enum spd_dimm_type dimm_type; + char part_number[SPD_DDR4_PART_LEN + 1]; + u8 serial_number[4]; + u8 bus_width; + u8 ranks; + u8 sdram_width; + u16 cap_per_die_mbit; + u16 size_mb; + u16 manufacturer_id; + u16 vdd_voltage; + bool ecc_extension; +} dimm_attr; + +typedef u8 spd_raw_data[512]; + +int spd_decode_ddr4(dimm_attr *dimm, spd_raw_data spd); + +enum cb_err spd_add_smbios17_ddr4(const u8 channel, const u8 slot, + const u16 selected_freq, + const dimm_attr *info); + +#endif /* DEVICE_DRAM_DDR4L_H */ |