diff options
| -rw-r--r-- | src/arch/riscv/trap_handler.c | 6 | ||||
| -rw-r--r-- | src/arch/riscv/trap_util.S | 19 |
2 files changed, 10 insertions, 15 deletions
diff --git a/src/arch/riscv/trap_handler.c b/src/arch/riscv/trap_handler.c index 842e3eab3b..288b05d1d1 100644 --- a/src/arch/riscv/trap_handler.c +++ b/src/arch/riscv/trap_handler.c @@ -69,7 +69,7 @@ void handle_supervisor_call(trapframe *tf) { } tf->gpr[10] = returnValue; write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j supervisor_call_return"); + asm volatile("j trap_return"); } static const char *const exception_names[] = { @@ -264,7 +264,7 @@ void handle_misaligned_load(trapframe *tf) { // return to where we came from write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j machine_call_return"); + asm volatile("j trap_return"); } void handle_misaligned_store(trapframe *tf) { @@ -292,5 +292,5 @@ void handle_misaligned_store(trapframe *tf) { // return to where we came from write_csr(mepc, read_csr(mepc) + 4); - asm volatile("j machine_call_return"); + asm volatile("j trap_return"); } diff --git a/src/arch/riscv/trap_util.S b/src/arch/riscv/trap_util.S index 5582a0770c..98db85c4cb 100644 --- a/src/arch/riscv/trap_util.S +++ b/src/arch/riscv/trap_util.S @@ -140,15 +140,10 @@ trap_entry: save_tf move a0,sp jal trap_handler - .global supervisor_call_return -supervisor_call_return: - csrr a0, mscratch - restore_regs - # go back into supervisor call - mret - .global machine_call_return -machine_call_return: - csrr a0, mscratch - restore_regs - # go back into machine call - mret + + .global trap_return +trap_return: + csrr a0, mscratch + restore_regs + # go back to the previous mode + mret |