diff options
| -rw-r--r-- | src/cpu/intel/socket_BGA956/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/cpu/intel/socket_mPGA478MN/Makefile.inc | 4 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/Kconfig | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/northbridge/intel/gm45/ram_calc.c | 14 |
5 files changed, 11 insertions, 15 deletions
diff --git a/src/cpu/intel/socket_BGA956/Makefile.inc b/src/cpu/intel/socket_BGA956/Makefile.inc index f33b409c15..05514a1548 100644 --- a/src/cpu/intel/socket_BGA956/Makefile.inc +++ b/src/cpu/intel/socket_BGA956/Makefile.inc @@ -8,11 +8,7 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -ifneq ($(CONFIG_POSTCAR_STAGE),y) -cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc -else cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S postcar-y += ../car/p4-netburst/exit_car.S -endif romstage-y += ../car/romstage.c diff --git a/src/cpu/intel/socket_mPGA478MN/Makefile.inc b/src/cpu/intel/socket_mPGA478MN/Makefile.inc index ef89ac65a1..78d7c0ee58 100644 --- a/src/cpu/intel/socket_mPGA478MN/Makefile.inc +++ b/src/cpu/intel/socket_mPGA478MN/Makefile.inc @@ -9,11 +9,7 @@ subdirs-y += ../microcode subdirs-y += ../hyperthreading subdirs-y += ../speedstep -ifneq ($(CONFIG_POSTCAR_STAGE),y) -cpu_incs-y += $(src)/cpu/intel/model_6ex/cache_as_ram.inc -else cpu_incs-y += $(src)/cpu/intel/car/core2/cache_as_ram.S postcar-y += ../car/p4-netburst/exit_car.S -endif romstage-y += ../car/romstage.c diff --git a/src/northbridge/intel/gm45/Kconfig b/src/northbridge/intel/gm45/Kconfig index 85902d36b2..193ec70ecb 100644 --- a/src/northbridge/intel/gm45/Kconfig +++ b/src/northbridge/intel/gm45/Kconfig @@ -29,6 +29,8 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select RELOCATABLE_RAMSTAGE select HAVE_LINEAR_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT select HAVE_VGA_TEXT_FRAMEBUFFER if MAINBOARD_DO_NATIVE_VGA_INIT + select POSTCAR_STAGE + select POSTCAR_CONSOLE config CBFS_SIZE hex diff --git a/src/northbridge/intel/gm45/Makefile.inc b/src/northbridge/intel/gm45/Makefile.inc index fdf0012ec4..c12bbf14ae 100644 --- a/src/northbridge/intel/gm45/Makefile.inc +++ b/src/northbridge/intel/gm45/Makefile.inc @@ -36,4 +36,6 @@ ramstage-y += gma.c smm-$(CONFIG_HAVE_SMI_HANDLER) += ../../../cpu/x86/lapic/apic_timer.c +postcar-y += ram_calc.c + endif diff --git a/src/northbridge/intel/gm45/ram_calc.c b/src/northbridge/intel/gm45/ram_calc.c index 71b5863e1b..011d90347b 100644 --- a/src/northbridge/intel/gm45/ram_calc.c +++ b/src/northbridge/intel/gm45/ram_calc.c @@ -118,9 +118,10 @@ void *cbmem_top(void) #define ROMSTAGE_RAM_STACK_SIZE 0x5000 -/* setup_stack_and_mtrrs() determines the stack to use after - * cache-as-ram is torn down as well as the MTRR settings to use. */ -void *setup_stack_and_mtrrs(void) +/* platform_enter_postcar() determines the stack to use after + * cache-as-ram is torn down as well as the MTRR settings to use, + * and continues execution in postcar stage. */ +void platform_enter_postcar(void) { struct postcar_frame pcf; uintptr_t top_of_ram; @@ -143,8 +144,7 @@ void *setup_stack_and_mtrrs(void) postcar_frame_add_mtrr(&pcf, top_of_ram - 4*MiB, 4*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram - 8*MiB, 4*MiB, MTRR_TYPE_WRBACK); - /* Save the number of MTRRs to setup. Return the stack location - * pointing to the number of MTRRs. - */ - return postcar_commit_mtrrs(&pcf); + run_postcar_phase(&pcf); + + /* We do not return here. */ } |